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ADSP-2181KST-133 Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-2181KST-133 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 32 page  ADSP-2181 –11– REV. D The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca- tion—you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spac- ing should be 0.1 x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie and Samtec. Target Memory Interface For your target system to be compatible with the EZ-ICE emu- lator, it must comply with the memory interface guidelines listed below. PM, DM, BM, IOM and CM Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM) and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the DSP’s data sheet. The performance of the EZ-ICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst case chip specifica- tion for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. De- pending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing require- ments within published limits. Restriction: All memory strobe signals on the ADSP-2181 ( RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 k Ω pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used. Target System Interface Signals When the EZ-ICE board is installed, the performance on some system signals changes. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: • EZ-ICE emulation introduces an 8 ns propagation delay be- tween your target circuitry and the DSP on the RESET signal. • EZ-ICE emulation introduces an 8 ns propagation delay be- tween your target circuitry and the DSP on the BR signal. • EZ-ICE emulation ignores RESET and BR when single- stepping. • EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). • EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP’s external memory bus only if bus grant ( BG) is asserted by the EZ-ICE board’s DSP. Target Architecture File The EZ-ICE software lets you load your program in its linked (executable) form. The EZ-ICE PC program can not load sec- tions of your executable located in boot pages (by the linker). With the exception of boot page 0 (loaded into PM RAM), all sections of your executable mapped into boot pages are not loaded. Write your target architecture file to indicate that only PM RAM is available for program storage, when using the EZ-ICE software’s loading feature. Data can be loaded to PM RAM or DM RAM. |
Número de pieza similar - ADSP-2181KST-133 |
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Descripción similar - ADSP-2181KST-133 |
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