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ASDP-21060LCW-160 Datasheet(Hoja de datos) 39 Page - Analog Devices

No. de Pieza. ASDP-21060LCW-160
Descripción  SHARC Processor
Descarga  64 Pages
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Fabricante  AD [Analog Devices]
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F
|
Page 39 of 64
|
March 2008
Link Ports —2 × CLK Speed Operation
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK:
Setup Skew = tLCLKTWH min – tDLDCH – tSLDCL
Hold skew is the maximum delay that can be introduced in
LCLK relative to LDATA:
Hold Skew = tLCLKTWL min – tHLDCH – tHLDCL
Calculations made directly from 2 speed specifications will
result in unrealistically small skew times because they include
multiple tester guardbands.
Note that link port transfers at 2× CLK speed at 40 MHz
(tCK = 25 ns) may fail. However, 2× CLK speed link port trans-
fers at 33 MHz (tCK = 30 ns) work as specified.
Table 25. Link Port Service Request Interrupts:1
u and 2u Speed Operations
5 V
3.3 V
Unit
Parameter
Min
Max
Min
Max
Timing Requirements
tSLCK
LACK/LCLK Setup Before CLKIN Low1
10
10
ns
tHLCK
LACK/LCLK Hold After CLKIN Low1
22ns
1 Only required for interrupt recognition in the current cycle.
Table 26. Link Ports—Receive
5 V
3.3 V
Unit
Parameter
Min
Max
Min
Max
Timing Requirements
tSLDCL
Data Setup Before LCLK Low
2.5
2.25
ns
tHLDCL
Data Hold After LCLK Low
2.25
2.25
ns
tLCLKIW
LCLK Period (2
u Operation)
tCK/2
tCK/2
ns
tLCLKRWL
LCLK Width Low1
4.5
5.25
ns
tLCLKRWH
LCLK Width High2
4.25
4
ns
Switching Characteristics
tDLAHC
LACK High Delay After CLKIN High3
18 + DT/2
28.5 + DT/2
18 + DT/2
29.5 + DT/2
ns
tDLALC
LACK Low Delay After LCLK High4
616
6
16
ns
1 For ADSP-21060L, specification is 5 ns min.
2 For ADSP-21062, specification is 4 ns min, for ADSP-21060LC, specification is 4.5 ns min.
3 LACK goes low with t
DLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
4 For ADSP-21060L, specification is 6 ns min, 18 ns max. For ADSP-21060C, specification is 6 ns min, 16.5 ns max. For ADSP-21060LC, specification is 6 ns min, 18.5 ns max.




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