TPS7A8300

SBVS197C – MAY 2013 – REVISED JULY 2013

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

DESCRIPTION

YYY is the package designator.

TPS7A8300YYYZ

Z is the package quantity.

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range, unless otherwise noted.

VALUE

MIN

MAX

UNIT

IN, BIAS, PG, EN

–0.3

+7.0

V

IN, BIAS, PG, EN (5% duty cycle)

–0.3

+7.5

V

Voltage

SNS, OUT

–0.3

(2)

V

NR/SS, FB

–0.3

+3.6

V

50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V

–0.3

V

OUT

Internally limited

A

Current

PG (sink current into device)

5

mA

–55

+150

°C

Temperature

–55

+150

°C

Human body model (HBM), JESD22-A114A

2

kV

Electrostatic discharge (ESD)

Charged device model (CDM), JESD22-C101B.01

500

V

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

(2)

(3)

ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TPS7A8300

RGW (QFN)

UNITS

20 PINS

Junction-to-ambient thermal resistance

35.7

Junction-to-case (top) thermal resistance

33.6

Junction-to-board thermal resistance

15.2

°C/W

Junction-to-top characterization parameter

0.4

Junction-to-board characterization parameter

15.4

Junction-to-case (bottom) thermal resistance

3.8

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

2

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