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ADSP-21489BSWZ-3A Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-21489BSWZ-3A Datasheet(HTML) 11 Page - Analog Devices |
11 / 68 page ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. B | Page 11 of 68 | March 2013 Delay Line DMA The processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. Scatter/Gather DMA The processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from non contiguous memory blocks. FFT Accelerator The FFT accelerator implements a radix-2 complex/real input, complex output FFT with no core intervention. The FFT accel- erator runs at the peripheral clock frequency. FIR Accelerator The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. IIR Accelerator The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coeffi- cients, a data memory for storing the intermediate data, and one MAC unit. A controller manages the accelerator. The IIR accel- erator runs at the peripheral clock frequency. Watchdog Timer The watchdog timer is used to supervise the stability of the sys- tem software. When used in this way, software reloads the watchdog timer in a regular manner so that the downward counting timer never expires. An expiring timer then indicates that system software might be out of control. The 32-bit watchdog timer that can be used to implement a soft- ware watchdog function. A software watchdog can improve system reliability by forcing the processor to a known state through generation of a system reset, if the timer expires before being reloaded by software. Software initializes the count value of the timer, and then enables the timer. The watchdog timer resets both the core and the internal peripherals. Note that this feature is available on the 176-lead package only. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the ADSP-2148x boots at system power-up from an 8-bit EPROM via the external port, an SPI master, or an SPI slave. Booting is determined by the boot con- figuration (BOOT_CFG2–0) pins in Table 9 for the 176-lead package and Table 10 for the 100-lead package. The “Running Reset” feature allows a user to perform a reset of the processor core and peripherals, but without resetting the PLL and SDRAM controller, or performing a boot. The functionality of the RESETOUT/RUNRSTIN pin has now been extended to also act as the input for initiating a Running Reset. For more information, see the ADSP-214xx SHARC Processor Hardware Reference. Power Supplies The processors have separate power supply connections for the internal (VDD_INT) and external (VDD_EXT) power supplies. The internal supply must meet the VDD_INT specifications. The external supply must meet the VDD_EXT specification. All exter- nal supply pins must be connected to the same power supply. To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDD_INT and GND. Static Voltage Scaling (SVS) Some models of the ADSP-2148x feature Static Voltage Scaling (SVS) on the VDD_INT power supply. (See the Ordering Guide on Page 66 for model details.) This voltage specification tech- nique can provide significant performance benefits including 450 MHz core frequency operation without a significant increase in power. SVS optimizes the required VDD_INT voltage for each individual device to enable enhanced operating frequency up to 450 MHz. The optimized SVS voltage results in a reduction of maximum IDD_INT which enables 450 MHz operation at the same or lower maximum power than 400 MHz operation at a fixed voltage supply. Implementation of SVS requires a specific voltage regu- lator circuit design and initialization code. Refer to the Engineer-to-Engineer Note “Static Voltage Scaling for ADSP-2148x Processors” (EE-357) for further information. The EE-Note details the requirements and process to implement a SVS power supply system to enable operation up to 450 MHz. This applies only to specific products within the ADSP-2148x family which are capable of supporting 450 MHz operation. Table 9. Boot Mode Selection, 176-Lead Package BOOT_CFG2–0 Booting Mode 000 SPI Slave Boot 001 SPI Master Boot 010 AMI User Boot (for 8-bit Flash Boot) 011 No boot (processor executes from internal ROM after reset) 1xx Reserved Table 10. Boot Mode Selection, 100-Lead Package BOOT_CFG1–0 Booting Mode 00 SPI Slave Boot 01 SPI Master Boot 10 Reserved 11 No boot (processor executes from internal ROM after reset) |
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