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ADSP-CM402F Datasheet(PDF) 9 Page - Analog Devices |
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ADSP-CM402F Datasheet(HTML) 9 Page - Analog Devices |
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9 / 84 page  Preliminary Technical Data Rev. PrE | Page 9 of 84 | September 2013 ADSP-CM402F/CM403F/CM407F/CM408F CODE and DATA (SRAM region in M4 space) in 64K byte blocks. Access to this region occurs at core clock speed, with no wait states. • Integrated Flash. This contains the 2M byte flash memory space interfaced via the SPI2 port of the processor. This memory space contains the application instructions and lit- eral (constant) data. Reads from flash memory are directly cached via internal code cache. Direct memory-mapped reads are permitted via SPI memory-mapped protocol. • Internal Code Cache. A zero-wait-state code cache SRAM memory is available internally (not visible in the memory map) to cache instruction access from internal flash as well as any externally connected serial flash and asynchronous memory. • MEM-X/MEM-Y. These are virtual memory blocks which are used as cacheable memory for the code cache. No phys- ical memory device resides inside these blocks. The application code must be compiled against these memory blocks to utilize the cache. SRAM Region Accesses in this region (0x2000_0000 to 0x3FFF_FFFF) are per- formed by the ARM Cortex-M4F core on its SYS interface. The SRAM region of the core can otherwise act as a data region for an application. • Internal SRAM Data Region. This space can contain read/write data. Internal SRAM can be partitioned between CODE and DATA (SRAM region in M4 space) in 64K byte blocks. Access to this region occurs at core clock speed, with no wait states. It supports read/write access by the M4F core and read/write DMA access by system devices. It supports exclusive memory accesses via the global exclusive access monitor within the ADI Cortex-M4F platform. Bit- banding support is also available. External (Memory-Mapped) Peripheral Region • External SPI Flash Support. Up to 16M byte of external serial quad flash memory optionally connected to the SPI0 port of the processor. Reads from flash memory are directly cached via internal code cache. Direct memory-mapped reads are permitted via SPI memory-mapped protocol. • System MMRs. Various system MMRs reside in this region. Bit-banding support is available for MMRs. External SRAM Region • L2 Asynchronous Memory. Up to 32M byte × 4 banks of external memory can be optionally connected to the asyn- chronous memory port (SMC). Code execution from these memory blocks can be optionally cached via internal code cache. Direct R/W data access is also possible. Figure 7. ADSP-CM40x Memory Map |
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