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SI5330H-A00221-GM Datasheet(PDF) 10 Page - Silicon Laboratories

No. de pieza SI5330H-A00221-GM
Descripción Electrónicos  Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs
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Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
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SI5330H-A00221-GM Datasheet(HTML) 10 Page - Silicon Laboratories

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Si5330
10
Rev. 1.0
5. Pin Descriptions
Note: Center pad must be tied to GND for normal operation.
Table 10. Si5330 Pin Descriptions
Pin #
Pin Name
I/O
Signal Type
Description
1IN1
I
Multi
Si5330A/B/C/G/H/J Differential Input Devices.
These pins are used as the differential clock input. IN1 is
the positive input; IN2 is the negative input. Refer to
“AN408: Termination Options for Any-Frequency, Any-
Output Clock Generators and Clock Buffers—Si5338,
Si5334, Si5330” for interfacing and termination details.
Si5330F/K/L/M Single-Ended Input Devices.
These pins are not used. Leave IN1 unconnected and
IN2 connected to ground.
2
IN2
I
Multi
3IN3
I
Multi
Si5330F/K/L/M Single-Ended Devices.
This is the single-ended clock input. Refer to AN408 for
interfacing and termination details.
Si5330A/B/C/G/H/J Differential Input Devices.
This pin is not used. Connect to ground.
4RSVD_GND
Ground.
Must be connected to system ground.
5RSVD_GND
Ground.
Must be connected to system ground.
6RSVD_GND
Ground.
Must be connected to system ground.
IN3
IN2
IN1
CLK2B
CLK2A
VDDO2
VDDO1
CLK1B
CLK1A
RSVD_GND
GND
GND
RSVD_GND
RSVD_GND
24
23
22
21
20
19
7
8
9
10
11
12


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