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LM5060 Datasheet(PDF) 11 Page - Texas Instruments |
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LM5060 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 33 page VIN VOUT STATUS UVLO OVP TIMER GND EN OUT SENSE GATE VIN LM5060 EN R8 R10 R11 RS Q1 C1 R4 GND GND nPGD High = Fault, Low= OK High = On, Low= Off R9 LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 Figure 21. Basic Application Circuit Functional Description The LM5060 is designed to drive an external high-side N-channel MOSFET. Over-Current protection is implemented by sensing the voltage drop across the MOSFET. When an adjustable voltage drop threshold is exceeded, and an adjustable time period has elapsed, the MOSFET is disabled. Over-Voltage Protection (OVP) and Under-Voltage Lock-Out (UVLO) monitoring of the input line is also provided. A low state on the enable pin will turn off the N-channel MOSFET and switch the LM5060 into a very low quiescent current off state. An active low power good output pin is provided to report the status of the N-channel MOSFET. The waiting time before the MOSFET is turned off after a fault condition is detected can be adjusted with an external timer capacitor. Since the LM5060 uses a constant current source to charge the gate of the external N-channel MOSFET, the output voltage rise time can be adjusted by adding external gate capacitance. This is useful when starting up into large capacitive loads. POWER-UP SEQUENCE The basic application circuit is shown in Figure 21 and a normal start-up sequence is shown in Figure 22. Start- up of the LM5060 is initiated when the EN pin is above the (ENTHH) threshold (2.0V). At start-up, the timer capacitor is charged with a 6 µA (typical) current source while the gate of the external N-channel MOSFET is charged through the GATE pin by a 24 µA (typical) current source. When the gate-to-source voltage (VGS) reaches the VGATE-TH threshold (typically 5V) the VGS sequence ends, the timer capacitor is quickly discharged to 0.3V, and begins charging the timer capacitor with a11 µA current source. The timer capacitor will charge until either the VDS Comparator indicates that the drain-to-source voltage (VDS) has been reduced to a nominal value (i.e. no fault) or the voltage on the timer capacitor has reached the VTMRH threshold (i.e. fault). The VDS Comparator monitors the voltage difference between the SENSE pin and the OUT pin. The SENSE pin voltage is user programmed to be lower than the input supply voltage by selecting a suitable sense resistor value. When the OUT pin voltage exceeds the voltage at the SENSE pin, the nPGD pin is asserted low (i.e. no fault) and the timer capacitor is discharged. STATUS CONDITIONS Output responses of the LM5060 to various input conditions is shown in Table 1. The input parameters include Enable (EN), Under-Voltage Lock-Out (UVLO), Over-Voltage Protection (OVP), input voltage (VIN), Start-Up Fault (VGS) and Run Fault (VDS) conditions. The output responses are the VIN pin current consumption, the GATE charge current, the TIMER capacitor charge (or discharge) current, the GATE discharge current if the timer capacitor voltage has reached the VTMRH threshold (typically 2V), as well as the status of nPGD. Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM5060 |
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