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AD9255BCPZ-125 Datasheet(PDF) 9 Page - Analog Devices |
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AD9255BCPZ-125 Datasheet(HTML) 9 Page - Analog Devices |
9 / 44 page Data Sheet AD9255 Rev. C | Page 9 of 44 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK setup time 0.30 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns SPI TIMING REQUIREMENTS1 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns 1 Refer to Figure 84 for a detailed timing diagram. Timing Diagrams tDCO tCH tCL tCLK CLK+ CLK– DCO– DCO/DCO+ D0/1+ TO D12/D13+ LVDS (DDR) MODE D0/1– TO D12/D13– CMOS MODE D0 TO D13 N – 1 N + 1 N + 2 N + 3 N + 5 N + 4 N VIN tA tSKEW tPD DEx – 12 DOx – 12 DEx – 11 DOx – 11 DEx – 10 DOx – 10 DEx – 9 DOx – 9 DEx – 8 DOx – 8 Dx – 12 Dx – 11 Dx – 10 Dx – 9 Dx – 8 NOTES 1. DEx DENOTES EVEN BIT. 2. DOx DENOTES ODD BIT. Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing SYNC CLK+ tHSYNC tSSYNC Figure 3. SYNC Input Timing Requirements |
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