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ADN4670BSTZ Datasheet(PDF) 4 Page - Analog Devices

No. de pieza ADN4670BSTZ
Descripción Electrónicos  Programmable Low Voltage 1:10 LVDS Clock Driver
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Fabricante Electrónico  AD [Analog Devices]
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ADN4670BSTZ Datasheet(HTML) 4 Page - Analog Devices

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ADN4670
Data Sheet
Rev. A | Page 4 of 12
LVDS SWITCHING CHARACTERISTICS
VDD = 2.375 V to 2.625 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max1
Unit
Conditions/Comments
Propagation Delay Low to High
tPLHx
2
3
ns
From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx
Propagation Delay High to Low
tPHLx
2
3
ns
From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx
Duty Cycle
tDUTY
45
55
%
From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx
Output Skew2
tSK(O)
30
ps
Any Qx/Qx
Pulse Skew3
tSK(P)
50
ps
Any Qx/Qx
Part-to-Part Output Skew4
tSK(PP)
600
ps
Any Qx/Qx
Output Rise Time
tr
350
ps
Any Qx/Qx, 20% to 80%, RL = 100 Ω CL = 5 pF
Output Fall Time
tf
350
Any Qx/Qx, 80% to 20%, RL = 100 Ω CL = 5 pF
Maximum Input Frequency
fCLK
900
1100
MHz
From CLK0/CLK0 or CLK1/ CLK1 to any Qx/Qx
1 Guaranteed by design and characterization.
2 Output skew is defined as the difference between the largest and smallest values of TPLHx within a device or the difference between the largest and smallest values of
TPHLx within a device, whichever of the two is greater.
3 Pulse skew is defined as the magnitude of the maximum difference between tPLH and tPHL for any channel of a device, that is, |tPHLx – tHLPx|.
4 Part-to-part output skew is defined as the difference between the largest and smallest values of TPLHx across multiple devices or the difference between the largest and
smallest values of TPHLx across multiple devices, whichever of the two is greater.
tPLH0
tPLH1
tPLH9
tPHL0
tPHL1
tPHL9
CLK
CLK
Q0
Q0
Q1
Q1
Q9
Q9
Figure 2. Waveforms for Calculation of tSK(O) and tSK(PP)


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