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ADSP-2191MKCA-160 Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-2191MKCA-160 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 52 page  –7– REV. 0 ADSP-2191M assigned a priority level of 11 are aliased to the lowest priority bit position (15) in these registers and share vector address 0x00 01E0. Interrupt routines can either be nested with higher priority inter- rupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The emulation, power-down, and reset interrupts are nonmaskable with the IMASK register, but software can use the DIS INT instruction to mask the power-down interrupt. The Interrupt Control (ICNTL) register controls interrupt nesting and enables or disables interrupts globally. The general-purpose Programmable Flag (PFx) pins can be con- figured as outputs, can implement software interrupts, and (as inputs) can implement hardware interrupts. Programmable Flag pin interrupts can be configured for level-sensitive, single edge-sensitive, or dual edge-sensitive operation. The IRPTL register is used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically main- tained during interrupt handling. To support interrupt, loop, and subroutine nesting, the PC stack is 33 levels deep, the loop stack is eight levels deep, and the status stack is 16 levels deep. To prevent stack overflow, the PC stack can generate a stack-level interrupt if the PC stack falls below three locations full or rises above 28 locations full. The following instructions globally enable or disable interrupt servicing, regardless of the state of IMASK. ENA INT; DIS INT; At reset, interrupt servicing is disabled. For quick servicing of interrupts, a secondary set of DAG and computational registers exist. Switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the DSP’s state. DMA Controller The ADSP-2191M has a DMA controller that supports automated data transfers with minimal overhead for the DSP core. Cycle stealing DMA transfers can occur between the ADSP-2191M’s internal memory and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interface. DMA-capa- ble peripherals include the Host port, SPORTs, SPI ports, and UART. Each individual DMA-capable peripheral has a dedicated DMA channel. To describe each DMA sequence, the DMA con- troller uses a set of parameters—called a DMA descriptor. When successive DMA sequences are needed, these DMA descriptors can be linked or chained together, so the completion of one DMA sequence auto-initiates and starts the next sequence. DMA sequences do not contend for bus access with the DSP core; instead DMAs “steal” cycles to access memory. Table 1. Interrupt Priorities/Addresses Interrupt IMASK/ IRPTL Vector Address1 1These interrupt vectors start at address 0x10000 when the DSP is in “no-boot,” run from external memory mode. Emulator (NMI)— Highest Priority NA NA Reset (NMI) 0 0x00 0000 Power-Down (NMI) 1 0x00 0020 Loop and PC Stack 2 0x00 0040 Emulation Kernel 3 0x00 0060 User Assigned Interrupt 4 0x00 0080 User Assigned Interrupt 5 0x00 00A0 User Assigned Interrupt 6 0x00 00C0 User Assigned Interrupt 7 0x00 00E0 User Assigned Interrupt 8 0x00 0100 User Assigned Interrupt 9 0x00 0120 User Assigned Interrupt 10 0x00 0140 User Assigned Interrupt 11 0x00 0160 User Assigned Interrupt 12 0x00 0180 User Assigned Interrupt 13 0x00 01A0 User Assigned Interrupt 14 0x00 01C0 User Assigned Interrupt— Lowest Priority 15 0x00 01E0 Table 2. Peripheral Interrupts and Priority at Reset Interrupt ID Reset Priority Slave DMA/Host Port Interface 0 0 SPORT0 Receive 1 1 SPORT0 Transmit 2 2 SPORT1 Receive 3 3 SPORT1 Transmit 4 4 SPORT2 Receive/SPI0 5 5 SPORT2 Transmit/SPI1 6 6 UART Receive 7 7 UART Transmit 8 8 Timer 0 9 9 Timer 1 10 10 Timer 2 11 11 Programmable Flag A (any PFx) 12 11 Programmable Flag B (any PFx) 13 11 Memory DMA port 14 11 Table 3. Interrupt Control (ICNTL) Register Bits Bit Description 0–3 Reserved 4Interrupt Nesting Enable 5Global Interrupt Enable 6 Reserved 7 MAC-Biased Rounding Enable 8–9 Reserved 10 PC Stack Interrupt Enable 11 Loop Stack Interrupt Enable 12–15 Reserved |
Número de pieza similar - ADSP-2191MKCA-160 |
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Descripción similar - ADSP-2191MKCA-160 |
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