SN54ABT162841, SN74ABT162841

20BIT BUSINTERFACE DTYPE LATCHES

WITH 3STATE OUTPUTS

SCBS665C − JUNE 1996 − REVISED JUNE 2004

3

POST OFFICE BOX 655303

logic diagram (positive logic)

1OE

To Nine Other Channels

1

56

55

2

1LE

1D1

C1

1D

1Q1

2OE

To Nine Other Channels

28

29

42

15

2LE

2D1

C1

1D

2Q1

−0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . .

30 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−18 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

64

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package

56

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54ABT162841

SN74ABT162841

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

VI

Input voltage

0

VCC

0

VCC

V

IOH

High-level output current

−3

−12

mA

IOL

Low-level output current

8

12

mA

∆t/∆v

Input transition rise or fall rate

Outputs enabled

10

10

ns/V

∆t/∆VCC

Power-up ramp rate

200

200

µs/V

TA

Operating free-air temperature

−55

125

−40

85

°C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.