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AD7305YR Datasheet(PDF) 8 Page - Analog Devices |
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AD7305YR Datasheet(HTML) 8 Page - Analog Devices |
8 / 20 page AD7304/AD7305 Rev. C | Page 8 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTB 1 VOUTA 2 VSS 3 VREFA 4 VOUTC 16 VOUTD 15 VDD 14 VREFC 13 VREFB 5 VREFD 12 GND 6 SDI/SHDN 11 LDAC 7 CLK 10 CLR 8 CS 9 AD7304 TOP VIEW (Not to Scale) Figure 8. AD7304 Pin Configuration Table 7. AD7304 Pin Function Descriptions Pin No. Mnemonic Description 1 VOUTB Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFB pin. Output is open circuit when SHDN is enabled. 2 VOUTA Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFA pin. Output is open circuit when SHDN is enabled. 3 VSS Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V. 4 VREFA Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation is VSS < VREFA < VDD. 5 VREFB Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation is VSS < VREFB < VDD. 6 GND Common Analog and Digital Ground. 7 LDAC Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 4 for operation. 8 CLR Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is not effected. 9 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to the decoded input register when CS returns high. Does not effect LDAC operation. 10 CLK Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS. 11 SDI/SHDN Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is present on VDD. 12 VREFD Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation is VSS < VREFD < VDD. 13 VREFC Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation is VSS VREFC < VDD. 14 VDD Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V. 15 VOUTD Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFD pin. Output is open circuit when SHDN is enabled. 16 VOUTC Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to VREFC pin. Output is open circuit when SHDN is enabled. |
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