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AD9786BSV Datasheet(PDF) 9 Page - Analog Devices |
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AD9786BSV Datasheet(HTML) 9 Page - Analog Devices |
9 / 56 page AD9786 Rev. B | Page 9 of 56 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 16 1 2 3 4 5 6 7 8 9 10 11 13 14 15 12 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1 IDENTIFIER 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DNC = DO NOT CONNECT CLKVDD DNC CLKVDD CLKGND CLK+ CLK– CLKGND DGND DVDD P1B15 P1B14 P1B13 P1B12 P1B11 P1B10 DGND DVDD P1B9 P1B8 P1B7 FSADJ REFIO RESET CSB SCLK SDIO SDO DGND DVDD P2B0 P2B1 P2B2 P2B3 P2B4 P2B5 DGND AD9786 TOP VIEW (Not to Scale) DVDD P2B6 P2B7 P2B8 Figure 2. Pin Configuration CLOCK Table 6. Clock Pin Function Descriptions Pin No. Mnemonic Direction Description 5, 6 CLK+, CLK– I Differential Clock Input. 2 DNC Do Not Connect. DCLKEXT 0x02[3] Mode 0 Pin configured for input of channel data rate or synchronizer clock. Internal clock synchronizer can be turned on or off with DCLKCRC (0x02[2]). 31 DATACLK I/O 1 Pin configured for output of channel data rate or synchronizer clock. 1, 3 CLKVDD Clock Domain 2.5 V. 4, 7 CLKGND Clock Domain 0 V. |
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