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AD9852ASQZ Datasheet(PDF) 7 Page - Analog Devices |
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AD9852ASQZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 52 page AD9852 Rev. E | Page 7 of 52 Test AD9852ASVZ AD9852ASTZ Parameter Temp Level Min Typ Max Min Typ Max Unit PARALLEL I/O TIMING CHARACTERISTICS tASU (Address Setup Time to WR Signal Active) Full IV 8.0 7.5 8.0 7.5 ns tADHW (Address Hold Time to WR Signal Inactive) Full IV 0 0 ns tDSU (Data Setup Time to WR Signal Inactive) Full IV 3.0 1.6 3.0 1.6 ns tDHD (Data Hold Time to WR Signal Inactive) Full IV 0 0 ns tWRLOW (WR Signal Minimum Low Time) Full IV 2.5 1.8 2.5 1.8 ns tWRHIGH (WR Signal Minimum High Time) Full IV 7 7 ns tWR (Minimum WR Time) Full IV 10.5 10.5 ns tADV (Address to Data Valid Time) Full V 15 15 15 15 ns tADHR (Address Hold Time to RD Signal Inactive) Full IV 5 5 ns tRDLOV (RD Low to Output Valid) Full IV 15 15 ns tRDHOZ (RD High to Data Three-State) Full IV 10 10 ns SERIAL I/O TIMING CHARACTERISTICS tPRE (CS Setup Time) Full IV 30 30 ns tSCLK (Period of Serial Data Clock) Full IV 100 100 ns tDSU (Serial Data Setup Time) Full IV 30 30 ns tSCLKPWH (Serial Data Clock Pulse Width High) Full IV 40 40 ns tSCLKPWL (Serial Data Clock Pulse Width Low) Full IV 40 40 ns tDHLD (Serial Data Hold Time) Full IV 0 0 ns tDV (Data Valid Time) Full V 30 30 ns CMOS LOGIC INPUTS 9 Logic 1 Voltage 25°C I 2.2 2.2 V Logic 0 Voltage 25°C I 0.8 0.8 V Logic 1 Current 25°C IV ± 5 ± 12 μA Logic 0 Current 25°C IV ± 5 ± 12 μA Input Capacitance 25°C V 3 3 pF POWER SUPPLY10 VS Current11 25°C I 815 922 585 660 mA VS Current12 25°C I 640 725 465 520 mA VS Current13 25°C I 585 660 425 475 mA PDISS 11 25°C I 2.70 3.20 1.93 2.39 W PDISS 12 25°C I 2.12 2.52 1.53 1.81 W PDISS 13 25°C I 1.93 2.29 1.40 1.65 W PDISS Power-Down Mode 25°C I 1 50 1 50 mW 1 The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied VDD or a 3 V TTL-level pulse input. 2 An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins. 3 Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are all 0s, the delay appears longer. This is due to insufficient phase accumulation per a system clock period to produce enough LSB amplitude to the D/A converter. 4 If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount. 5 The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks. 6 A change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold. 7 Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075. 8 Comparator input originates from analog output section via external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω. 9 Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 3.) 10 If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal Considerations section for derating and thermal management information. 11 All functions engaged. 12 All functions except inverse sinc engaged. 13 All functions except inverse sinc and digital multipliers engaged. |
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