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ADP2108ACBZ-2.5-R7 Datasheet(PDF) 11 Page - Analog Devices |
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ADP2108ACBZ-2.5-R7 Datasheet(HTML) 11 Page - Analog Devices |
11 / 20 page Data Sheet ADP2108 Rev. G | Page 11 of 20 THEORY OF OPERATION Figure 29. Functional Block Diagram The ADP2108 is a step-down dc-to-dc converter that uses a fixed frequency and high speed current mode architecture. The high switching frequency allows for a small step-down, dc-to-dc converter solution. The ADP2108 operates with an input voltage of 2.3 V to 5.5 V and regulates an output voltage down to 1.0 V. CONTROL SCHEME The ADP2108 operates with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency, but shifts to a power save mode control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in power save mode at light loads, the output voltage is controlled in a hysteretic manner, with higher VOUT ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. PWM MODE In PWM mode, the ADP2108 operates at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, the PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFET switch and turns on the NFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The ADP2108 regulates the output voltage by adjusting the peak inductor current threshold. POWER SAVE MODE The ADP2108 smoothly transitions to the power save mode of operation when the load current decreases below the power save mode current threshold. When the ADP2108 enters power save mode, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the ADP2108 enters an idle mode. COUT discharges until VOUT falls to the PWM regulation voltage, at which point the device drives the inductor to make VOUT rise again to the upper threshold. This process is repeated while the load current is below the power save mode current threshold. Power Save Mode Current Threshold The power save mode current threshold is set to 80 mA. The ADP2108 employs a scheme that enables this current to remain accurately controlled, independent of VIN and VOUT levels. This scheme also ensures that there is very little hysteresis between the power save mode current threshold for entry to and exit from the power save mode. The power save mode current threshold is optimized for excellent efficiency over all load currents. ENABLE/SHUTDOWN The ADP2108 starts operation with soft start when the EN pin is toggled from logic low to logic high. Pulling the EN pin low forces the device into shutdown mode, reducing the shutdown current below 1 μA. GND FB VIN SW EN ADP2108 SOFT START UNDERVOLTAGE LOCKOUT OSCILLATOR THERMAL SHUTDOWN DRIVER AND ANTISHOOT- THROUGH PSM COMP LOW CURRENT PWM COMP ILIMIT GM ERROR AMP PWM/ PSM CONTROL |
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