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NM25C041 Datasheet(PDF) 3 Page - Fairchild Semiconductor

No. de Pieza. NM25C041
Descripción  4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI™) Synchronous Bus)
Descarga  10 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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NM25C041 Datasheet(HTML) 3 Page - Fairchild Semiconductor

 
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NM25C041 Rev. D.1
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature
-65
°C to +150°C
All Input or Output Voltages
+6.5V to -0.3V
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
+300
°C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM25C041
0
°C to +70°C
NM25C041E
-40
°C to +85°C
NM25C041V
-40
°C to +125°C
Power Supply (VCC)
NM25C041
4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V
≤ V
CC ≤ 5.5V
Symbol
Parameter
Conditions
Min
Max
Units
I
CC
Operating Current
CS = V
IL
3mA
I
CCSB
Standby Current
CS = V
CC
50
µA
IIL
Input Leakage
VIN = 0 to VCC
-1
1
µA
I
OL
Output Leakage
V
OUT = GND to VCC
-1
1
µA
V
IL
Input Low Voltage
-0.3
V
CC * 0.3
V
V
IH
Input High Voltage
0.7 * V
CC
V
CC + 0.3
V
VOL
Output Low Voltage
IOL = 1.6 mA
0.4
V
V
OH
Output High Voltage
I
OH = -0.8 mA
V
CC - 0.8
V
f
OP
SCK Frequency
2.1
MHz
t
RI
Input Rise Time
2.0
µs
tFI
Input Fall Time
2.0
µs
t
CLH
Clock High Time
(Note 2)
190
ns
t
CLL
Clock Low Time
(Note 2)
190
ns
t
CSH
Min CS High Time
(Note 3)
240
ns
tCSS
CS Setup Time
240
ns
t
DIS
Data Setup Time
100
ns
t
HDS
HOLD Setup Time
90
ns
t
CSN
CS Hold Time
240
ns
tDIN
Data Hold Time
100
ns
t
HDN
HOLD Hold Time
90
ns
t
PD
Output Delay
C
L = 200 pF
240
ns
t
DH
Output Hold Time
0
ns
tLZ
HOLD to Output Low Z
100
ns
t
DF
Output Disable Time
C
L = 200 pF
240
ns
t
HZ
HOLD to Output High Z
100
ns
t
WP
Write Cycle Time
1–4 Bytes
10
ms
Capacitance (Note 4) T
A = 25°C, f = 2.1/1 MHz
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
38
pF
C
IN
Input Capacitance
2
6
pF
AC Test Conditions
Output Load
CL = 200 pF
Input Pulse Levels
0.1 * V
CC - 0.9 * VCC
Timing Measurement Reference Level
0.3 * VCC - 0.7 * VCC
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The f
OP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and t
CLH = 190ns, tCLL must be 286ns.
Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.


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