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NM25C640 Datasheet(Hoja de datos) 3 Page - Fairchild Semiconductor

No. de Pieza. NM25C640
Descripción  64K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Descarga  10 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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NM25C640 Rev. D.2
Standard Voltage 4.5
V
CC 5.5V Specifications
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature
-65
°C to +150°C
All Input or Output Voltage with
Respect to Ground
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300
°C
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
NM25C640
0
°C to +70°C
NM25C640E
-40
°C to +85°C
NM25C640V
-40
°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V
≤ V
CC ≤ 5.5V (unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
I
CC
Operating Current
CS = V
IL
3mA
ICCSB
Standby Current
CS = VCC
50
µA
I
IL
Input Leakage
V
IN = 0 to VCC
-1
+1
µA
IOL
Output Leakage
VOUT = GND to VCC
-1
+1
µA
V
IL
CMOS Input Low Voltage
-0.3
V
CC * 0.3
V
V
IH
CMOS Input High Voltage
V
CC * 0.7
V
CC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH = -0.8 mA
V
CC - 0.8
V
fOP
SCK Frequency
2.75
MHz
t
RI
Input Rise Time
2.0
µs
t
FI
Input Fall Time
2.0
µs
t
CLH
Clock High Time
(Note 2)
155
ns
t
CLL
Clock Low Time
(Note 2)
155
ns
tCSH
Min CS High Time
(Note 3)
240
ns
t
CSS
CS Setup Time
176
ns
tDIS
Data Setup Time
50
ns
t
HDS
HOLD Setup Time
90
ns
t
CSN
CS Hold Time
155
ns
t
DIN
Data Hold Time
50
ns
t
HDN
HOLD Hold Time
90
ns
tPD
Output Delay
CL = 200 pF
135
ns
t
DH
Output Hold Time
0
ns
tLZ
HOLD to Output Low Z
240
ns
t
DF
Output Disable Time
C
L = 200 pF
290
ns
t
HZ
HOLD to Output High Z
240
ns
tWP
Write Cycle Time
1–32 Bytes
10
ms
Capacitance T
A = 25°C, f = 2.1/1 MHz (Note 4)
Symbol
Test
Typ Max Units
C
OUT
Output Capacitance
3
8
pF
C
IN
Input Capacitance
2
6
pF
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The f
OP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and t
CLH = 190ns, tCLL must be 286ns.
Note 3: CS must be brought high for a minimum of t
CSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Output Load
C
L = 200 pF
Input Pulse Levels
0.1 * V
CC – 0.9 * VCC
Timing Measurement Reference Level
0.3 * VCC - 0.7 • VCC




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