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NM25C640 Datasheet(PDF) 1 Page - Fairchild Semiconductor

No. de Pieza. NM25C640
Descripción  64K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
Descarga  10 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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NM25C640 Datasheet(HTML) 1 Page - Fairchild Semiconductor

 
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NM25C640 Rev. D.2
PRELIMINARY
March 1999
© 1999 Fairchild Semiconductor Corporation
NM25C640
64K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C640 is a 65,536-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C640 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C640 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
Features
s 2.75 MHz clock rate @ 4.5V to 5.5V
2.1 MHz @ 2.7V to 4.5V
s 65,536 bits organized as 8,192 x 8
s Multiple chips on the same 3-wire bus with separate chip
select lines
s Self-timed programming cycle
s Simultaneous programming of 1 to 32 bytes at a time
s Status register can be polled during programming to monitor
READY/BUSY
s Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
s Block write protect feature to protect against accidental
writes
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP or 8-Pin SO
DS500041-1
Instruction
Decoder
Control Logic
and Clock
Generators
High Voltage
Generator
and
Program
Timer
Instruction
Register
Program
Enable
Data In/Out Register
8 Bits
Data Out
Buffer
Non-Volatile
Status Register
Decoder
1 of 8,192
Address
Counter/
Register
EEPROM Array
65,536 Bits
(8,192 x 8)
Read/Write Amps
CS
HOLD
SCK
VCC
VSS
VPP
WP
SI
SO


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