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AD7228ABP Datasheet(PDF) 4 Page - Analog Devices |
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AD7228ABP Datasheet(HTML) 4 Page - Analog Devices |
4 / 8 page AD7228A REV. A –4– ABSOLUTE MAXIMUM RATINGS 1 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V Digital Input Voltage to GND . . . . . . . . . . . . . . . –0.3 V, VDD VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V, VDD VOUT to GND 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V SS, VDD Power Dissipation (Any Package) to +75 °C . . . . . . . 1000 mW Derates above 75 °C by . . . . . . . . . . . . . . . . . . . . 2.0 mW/°C Operating Temperature Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40 °C to +85°C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40 °C to +85°C Extended . . . . . . . . . . . . . . . . . . . . . . . . . –55 °C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65 °C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300 °C NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Outputs may be shorted to any voltage in the range V SS to VDD provided that the power dissipation of the package is not exceeded. Typical short circuit current for a short to GND or VSS is 50 mA. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7228A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS DIP AND SOIC PLCC ORDERING GUIDE Total Temperature Unadjusted Package Model1 Range Error (LSB) Option2 AD7228ABN –40 °C to +85°C ±2 max N-24 AD7228ACN –40 °C to +85°C ±1 max N-24 AD7228ABP –40 °C to +85°C ±2 max P-28A AD7228ACP –40 °C to +85°C ±1 max P-28A AD7228ABR –40 °C to +85°C ±2 max R-24 AD7228ACR –40 °C to +85°C ±1 max R-24 AD7228ABQ –40 °C to +85°C ±2 max Q-24 AD7228ACQ –40 °C to +85°C ±1 max Q-24 AD7228ATQ 3 –55 °C to +125°C ±2 max Q-24 AD7228AUQ 3 –55 °C to +125°C ±1 max Q-24 NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local sales office for military data sheet and availability. 2N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC (SOIC). 3These grades will be available to /883B processing only. CIRCUIT INFORMATION D/A SECTION The AD7228A contains eight identical, 8-bit, voltage-mode digital-to-analog converters. The output voltages from the con- verters have the same polarity as the reference voltage, allowing single supply operation. A novel DAC switch pair arrangement on the AD7228A allows a reference voltage range from +2 V to +10 V when operated from a VDD of +15 V. Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high-speed NMOS switches. The simplified circuit diagram for one channel is shown in Figure 3. Note that VREF and GND are common to all eight DACs. Figure 3. D/A Simplified Circuit Diagram The input impedance at the VREF pin of the AD7228A is the parallel combination of the eight individual DAC reference in- put impedances. It is code dependent and can vary from 2 k Ω to infinity. The lowest input impedance occurs when all eight DACs are loaded with digital code 01010101. Therefore, it is important that the external reference source presents a low out- put impedance to the VREF terminal of the AD7228A under changing load conditions. Due to transient currents at the refer- ence input during digital code changes a 0.1 µF (or greater) decoupling capacitor is recommended on the VREF input for dc applications. The nodal capacitance at the reference terminal is also code dependent and typically varies from 120 pF to 350 pF. Each VOUT pin can be considered as a digitally programmable voltage source with an output voltage: VOUTN = DN • VREF where DN is a fractional representation of the digital input code and can vary from 0 to 255/256. The output impedance is that of the output buffer amplifier as described in the following section. |
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