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NM93C06 Datasheet(PDF) 6 Page - Fairchild Semiconductor

No. de Pieza. NM93C06
Descripción  256-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Descarga  13 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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NM93C06 Datasheet(HTML) 6 Page - Fairchild Semiconductor

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NM93C06 Rev. E
Functional Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (“1”) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 6-bit address information
should be issued. For certain instructions, some of these 6 bits are
don’t care values (can be “0” or “1”), but they should still be issued.
Following the address information, depending on the instruction
(WRITE and WRALL), 16-Bit data is issued. Otherwise, depend-
ing on the instruction (READ), the device starts to drive the output
data on the DO line. Other instructions perform certain control
functions and do not deal with data bits. The Microwire cycle ends
when the CS signal is brought low. However during certain
instructions, falling edge of the CS signal initiates an internal cycle
(Programming), and the device remains busy till the completion of
the internal cycle. Each of the 7 instructions is explained in detail
in the following sections.
1) Read (READ)
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. Refer
Read cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it “powers up” in the Write Disable
(WDS) state. Therefore, all programming operations must be
preceded by a Write Enable (WEN) instruction. Once a Write
Enable instruction is executed, programming remains enabled
until a Write Disable (WDS) instruction is executed or V
CC is
completely removed from the part. Input information (Start bit,
Opcode and Address) for this WEN instruction should be issued
as listed under Table1. The device becomes write-enabled at the
end of this cycle when the CS signal is brought low. Execution of
a READ instruction is independent of WEN instruction. Refer
Write Enable cycle diagram.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only when
I Device is write-enabled (Refer WEN instruction)
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after tCS interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer
Write cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvert-
ent writes etc.
4) Write All (WRALL)
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when
I Device is write-enabled (Refer WEN instruction)
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
WP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer
Write All
cycle diagram.
5) Write Disable (WDS)
Write Disable (WDS) instruction disables all programming opera-
tions and should follow all programming operations. Executing this
instruction after a valid write instruction would protect against
accidental data disturb due to spurious noise, glitches, inadvertent
writes etc. Input information (Start bit, Opcode and Address) for this
WDS instruction should be issued as listed under Table1. The
device becomes write-disabled at the end of this cycle when the CS
signal is brought low. Execution of a READ instruction is indepen-
dent of WDS instruction. Refer
Write Disable cycle diagram.
6) Erase (ERASE)
The ERASE instruction will program all bits in the specified
location to a logical “1” state. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. After inputting the last bit of data (A0 bit), CS signal
must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming
cycle. It takes t
WP time (Refer appropriate DC and AC Electrical
Characteristics table) for the internal programming cycle to finish.
During this time, the device remains busy and is not ready for
another instruction. Status of the internal programming can be
polled as described under WRITE instruction description. While
the device is busy, it is recommended that no new instruction be
issued. Refer
Erase cycle diagram.


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