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NM93C66A Datasheet(PDF) 5 Page - Fairchild Semiconductor

No. de Pieza. NM93C66A
Descripción  4K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)
Descarga  13 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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NM93C66A Datasheet(HTML) 5 Page - Fairchild Semiconductor

 
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NM93C66A Rev. E.1
Pin Description
Chip Select (CS)
This is an active high input pin to NM93C66A EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Serial Input (DI)
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Organization (ORG)
This is an input pin to the device and is used to select the format
of data (16-bit or 8-bit). If this pin is tied high, 16-bit format is
selected, while if it is tied low, 8-bit format is selected. Depending
on the format selected, NM93C66A requires 8-bit address field
(for 16-bit data format) or 9-bit address field (for 8-bit data format).
Refer Table 1 and Table 2 for more details. This pin is internally
pulled-up to VCC. Hence leaving this pin unconnected would
default to 16-bit data format.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array, a set of 7 instructions are implemented on
NM93C66A. The format of each instruction is listed under Table
1 (for 16-bit format) and Table 2 (for 8-bit format).
Instruction
Each of the above 7 instructions is explained under individual
instruction descriptions.
Start bit
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with 2 MSB of address field) select a
particular instruction to be executed.
Address Field
Depending on the selected organization, this is a 8-bit or 9-bit field
and should immediately follow the Opcode bits. In NM93C66A, all
8 bits (or 9 bits) are used for address decoding during READ,
WRITE and ERASE instructions. During all other instructions, the
MSB 2 bits are used to decode instruction (along with Opcode bits).
Data Field
Depending on the selected organization, this is a 16-bit or 8-bit
field and should immediately follow the Address bits. Only the
WRITE and WRALL instructions require this field. MSB bit (D15 or
D7) is clocked first and LSB bit (D0) is clocked last (both during
writes as well as reads).
Table 1. Instruction set (16-bit organization)
Instruction
Start Bit
Opcode Field
Address Field
Data Field
READ
1
10
A7
A6
A5
A4
A3
A2
A1
A0
WEN
1
00
1
1
XXXXXX
WRITE
1
01
A7
A6
A5
A4
A3
A2
A1
A0
D15-D0
WRALL
1
00
0
1
XXXXXX
D15-D0
WDS
1
00
0
0
XXXXXX
ERASE
1
11
A7
A6
A5
A4
A3
A2
A1
A0
ERAL
1
00
1
0
XXXXXX


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