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TMP275 Datasheet(PDF) 9 Page - Texas Instruments |
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TMP275 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 19 page TMP275 SBOS363D − JUNE 2006 − REVISED AUGUST 2007 www.ti.com 9 its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP275 loses the arbitration, its ALERT pin will remain active. GENERAL CALL The TMP275 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device acknowledges the General Call address and responds to commands in the second byte. If the second byte is 00000100, the TMP275 latches the status of the address pins, but does not reset. If the second byte is 00000110, the TMP275 latches the status of the address pins and resets the internal registers to the power-up values. HIGH-SPEED MODE In order for the Two-Wire bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP275 will not acknowledge this byte, but will switch its input filters on SDA and SCL and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master transmits a Two-Wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP275 switches the input and output filters back to fast-mode operation. TIMEOUT FUNCTION The TMP275 resets the serial interface if either SCL or SDA is held LOW for 54ms (typ) between a START and STOP condition. The TMP275 releases the bus if it is pulled LOW and waits for a START condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1kHz for SCL operating frequency. TIMING DIAGRAMS The TMP275 is Two-Wire and SMBus-compatible. Figure 4 to Figure 7 describe the various operations on the TMP275. Bus definitions are given below. Parameters for Figure 4 are defined in Table 12. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave. PARAMETER FAST MODE HIGH-SPEED MODE UNITS PARAMETER MIN MAX MIN MAX UNITS SCL Operating Frequency f(SCL) 0.001 0.4 0.001 3.4 MHz Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns Hold time after repeated START condition. After this period, the first clock is generated. t(HDSTA) 100 100 ns Repeated START Condition Setup Time t(SUSTA) 100 100 ns STOP Condition Setup Time t(SUSTO) 100 100 ns Data Hold Time t(HDDAT) 0 0 ns Data Setup Time t(SUDAT) 100 10 ns SCL Clock LOW Period t(LOW) 1300 160 ns SCL Clock HIGH Period t(HIGH) 600 60 ns Clock/Data Fall Time tF 300 160 ns Clock/Data Rise Time tR 300 160 ns for SCLK ≤ 100kHz tR 1000 ns Table 12. Timing Diagram Definitions for the TMP275 |
Número de pieza similar - TMP275 |
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Descripción similar - TMP275 |
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