VTH(POR)

Internally Set

Vin

Vout

PG

CT

CT

CT

C

1V

t

1 A

´

=

m

TPS7A6601-Q1, TPS7A6633-Q1

TPS7A6650-Q1, TPS7A6933-Q1

TPS7A6950-Q1

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SLVSBL0B – DECEMBER 2012 – REVISED AUGUST 2013

An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output

current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this

pin is open, the default delay time is 150 µs (typ). After releasing the nRST pin high, the capacitor on this pin

discharges, thus allowing the capacitor to charge from approx 0.2 V for the next power-on-reset delay-timer

function.

(1)

The power-on-reset initializes once the output Vout exceeds 90% of the programmed value. The power-on-reset

delay is a function of the value set by an external capacitor on the CT pin before the releasing of the PG terminal

high.

Figure 19. Conditions for Activation of Reset

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