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TPS2321IPWR Datasheet(PDF) 3 Page - Texas Instruments

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No. de Pieza. TPS2321IPWR
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TPS2321IPWR Datasheet(HTML) 3 Page - Texas Instruments

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DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-
clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When the
controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When
the ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 µs,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls FAULT low. The
other channel will run normally if not in overcurrent. In order to turn the channel back on, either the enable pin
has to be toggled or the input power has to be cycled.
GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15
μA to each.
The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the
turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These
capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up.
The charge-pump circuitry will generate gate-to-source voltages of 9 V-12 V across the external MOSFET
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GATE1 and GATE2, respectively. The TPS2320/TPS2321 draws its operating current
from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement
overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates
an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws
50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also
connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An
overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2.
To ensure proper circuit breaker operation, VI(ISENSE1) and VI(ISET1) should never exceed VI(IN1). Similarly,
VI(ISENSE2) and VI(ISET2) should never exceed VI(IN2).
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to
restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is
used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-
μF ceramic capacitor should
be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the
device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry
and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than5.5 V,
VREG and IN1 may be connected together. However, under these conditions, disabling the device will not place
the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed,
thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-
μF ceramic
capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1
μF to 10μF.
Copyright © 2000–2013, Texas Instruments Incorporated
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