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SN74GTLP1395PWR Datasheet(PDF) 3 Page - Texas Instruments |
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SN74GTLP1395PWR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 24 page www.ti.com FUNCTIONAL DESCRIPTION SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C–JUNE 2001–REVISED JANUARY 2006 The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY, and 2T/C control 2A, 2B, and 2Y. OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high, the B-port output is disabled. A separate LVTTL A input and Y output provide a feedback path for control and diagnostics monitoring. OEBY controls the Y output. When OEBY is low, the Y output is active. When OEBY is high, the Y output is disabled. T/C selects polarity of data transmission in both directions. When T/C is high, data transmission is true, and A data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary, and inverted A data goes to the B bus and inverted B data goes to the Y bus. FUNCTION TABLES abc OUTPUT CONTROL INPUTS OUTPUT MODE T/C OEAB OEBY X H H Z Isolation H L H A data to B bus True transparent H H L B data to Y bus True transparent H L L A data to B bus, B data to Y bus with feedback path L L H Inverted A data to B bus Inverted transparent L H L Inverted B data to Y bus Inverted A data to B bus, Inverted transparent LL L Inverted B data to Y bus with feedback path OUTPUT EDGE-RATE CONTROL (ERC) INPUT OUTPUT ERC B-PORT LOGIC LEVEL EDGE RATE H Slow LFast 3 |
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