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ADSP-21479KCPZ-1A Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-21479KCPZ-1A Datasheet(HTML) 5 Page - Analog Devices |
5 / 76 page ADSP-21477/ADSP-21478/ADSP-21479 Rev. C | Page 5 of 76 | July 2013 buses and on-chip instruction cache, the processor can simulta- neously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The processor’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction. Variable Instruction Set Architecture (VISA) In addition to supporting the standard 48-bit instructions from previous SHARC processors, the processors support new instructions of 16 and 32 bits. This feature, called Variable Instruction Set Architecture (VISA), drops redundant/unused Figure 2. SHARC Core Block Diagram S SIMD Core CACHE INTERRUPT 5 STAGE PROGRAM SEQUENCER PM ADDRESS 32 DM ADDRESS 32 DM DATA 64 PM DATA 64 DAG1 16×32 MRF 80-BIT ALU MULTIPLIER SHIFTER RF Rx/Fx PEx 16×40-BIT JTAG DMD/PMD 64 ASTATx STYKx ASTATy STYKy TIMER RF Sx/SFx PEy 16×40-BIT MRB 80-BIT MSB 80-BIT MSF 80-BIT FLAG SYSTEM I/F USTAT 4×32-BIT PX 64-BIT DAG2 16×32 ALU MULTIPLIER SHIFTER DATA SWAP PM ADDRESS 24 PM DATA 48 |
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