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AD669 Datasheet(PDF) 8 Page - Analog Devices |
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AD669 Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page AD669 REV. A –8– OUTPUT SETTLING AND GLITCH The AD669’s output buffer amplifier typically settles to within 0.0008% FS (l/2 LSB) of its final value in 8 µs for a full-scale step. Figures 7a and 7b show settling for a full-scale and an LSB step, respectively, with a 2 k Ω, 1000 pF load applied. The guar- anteed maximum settling time at +25 °C for a full-scale step is 13 µs with this load. The typical settling time for a 1 LSB step is 2.5 µs. The digital-to-analog glitch impulse is specified as 15 nV-s typi- cal. Figure 7c shows the typical glitch impulse characteristic at the code 011 . . . 111 to 100 . . . 000 transition when loading the second rank register from the first rank register. 20 –10 0 0 +10 10 600 400 200 0 –200 –400 –600 µs a. –10 V to +10 V Full-Scale Step Settling 5 0 0 600 400 200 –200 –400 –600 µs 1 23 4 b. LSB Step Settling 5 0 0 +10 –10 µs 1 23 4 c. D-to-A Glitch Impulse Figure 7. Output Characteristics DIGITAL CIRCUIT DETAILS The bus interface logic of the AD669 consists of two indepen- dently addressable registers in two ranks. The first rank consists of a 16-bit register which is loaded directly from a 16-bit micro- processor bus. Once the 16-bit data word has been loaded in the first rank, it can be loaded into the 16-bit register of the second rank. This double-buffered organization avoids the generation of spurious analog output values. The first rank latch is controlled by CS and L1. Both of these inputs are active low and are level-triggered. This means that data present during the time when both CS and L1 are low will enter the latch. When either one of these signals returns high, the data is latched. The second rank latch is controlled by LDAC. This input is ac- tive high and is also level-triggered. Data that is present when LDAC is high will enter the latch, and hence the DAC will change state. When this pin returns low, the data is latched in the DAC. Note that LDAC is not gated with CS or any other control sig- nal. This makes it possible to simultaneously update all of the AD669’s present in a multi-DAC system by tying the LDAC pins together. After the first rank register of each DAC has been individually loaded and latched, the second rank registers are then brought high together, updating all of the DACs at the same time. To reduce bit skew, it is suggested to leave 100 ns between the first rank load and the second rank load. The first rank latch and second rank latch can be used together in a master-slave or edge-triggered configuration. This mode of operation occurs when LDAC and CS are tied together with L1 tied to ground. Rising edges on the LDAC-CS pair will update the DAC with the data presented preceding the edge. The tim- ing diagram for operation in this mode can be seen in Figure lb. Note, however, that the sum of tLOW and tHIGH must be long enough to allow the DAC output to settle to its new value. Table I. AD669 Truth Table CS L1 LDAC Operation 0 0 X First Rank Enable X 1 X First Rank Latched 1 X X First Rank Latched X X 1 Second Rank Enabled X X 0 Second Rank Latched 0 0 1 All Latches Transparent “X” = Don’t Care It is possible to make the second rank register transparent by ty- ing Pin 23 high. Any data appearing in the first rank register will then appear at the output of the DAC. It should be noted, how- ever, that the deskewing provided by the second rank latch is then defeated, and glitch impulse may increase. If it is desired to make both registers transparent, this can be done by tying Pins 5 and 6 low and Pin 23 high. Table I shows the truth table for the AD669, while the timing diagram is found in Figure 1. INPUT CODING The AD669 uses positive-true binary input coding. Logic “1” is represented by an input voltage greater than 2.0 V, and Logic “0” is defined as an input voltage less than 0.8 V. |
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