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HCPL-0708 Datasheet(PDF) 10 Page - AVAGO TECHNOLOGIES LIMITED |
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HCPL-0708 Datasheet(HTML) 10 Page - AVAGO TECHNOLOGIES LIMITED |
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10 / 12 page  10 Application Information Bypassing and PC Board Layout The HCPL-0708 optocoupler is extremely easy to use. No external interface circuitry is required because the HCPL- 0708 uses high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. Figure 6. Recommended printed circuit board layout. Figure 7. Recommended printed circuit board layout. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a sys- tem. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low Figure 8. INPUT tPLH tPHL OUTPUT IF VO 10% 90% 90% 10% VOH VOL 0 mA 50% 12 mA 2.5 V CMOS 7 5 6 8 2 3 4 1 GND C NC VDD VO IF C1, C2 = 0.01 µF TO 0.1 µF VDD C2 VO GND IF C1, C2 = 0.01 µF TO 0.1 µF As shown in Figure 6, the only external component re- quired for proper operation is the bypass capacitor. Ca- pacitor values should be between 0.01 µF and 0.1 µF. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 7 illustrates the recommended printed circuit board layout for the HPCL-0708. to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See Figure 8. |
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Descripción similar - HCPL-0708 |
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