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TPS2301IPWRG4 Datasheet(PDF) 5 Page - Texas Instruments

No. de Pieza. TPS2301IPWRG4
Descripción  DUAL HOT-SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
Descarga  25 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS2301IPWRG4 Datasheet(HTML) 5 Page - Texas Instruments

 
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TPS2300
TPS2301
www.ti.com
SLVS265H – FEBRUARY 2000 – REVISED JULY 2013
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VI(IN1), VI(ISENSE1), VI(VSENSE1), VI(VSENSE2), VI(ISET1)
3
13
VI(IN2), VI(ISENSE2), VI(ISET2), VI(VREG)
3
5.5
VI
Input voltage
V
VI(ISENSE1), VI(ISET1), VI(VSENSE1)
VI(IN1)
VI(ISENSE2), VI(ISET2), VI(VSENSE2)
VI(IN2)
TJ
Operating virtual junction temperature
–40
100
°C
ELECTRICAL CHARACTERISTICS
over recommended operating temperature range (–40°C < TA < 85°C), 3 V ≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
II(IN1)
Input current, IN1
VI(ENABLE) = 5 V (TPS2301),
0.5
1
mA
II(IN2)
Input current, IN2
VI(ENABLE) = 0 V (TPS2300)
75
200
µA
Standby current (sum of
currents into IN1, IN2,
VI(ENABLE) = 0 V (TPS2301),
II(stby)
5
µA
ISENSE1, ISENSE2,
VI(ENABLE) = 5 V (TPS2300)
ISET1, and ISET2)
GATE1
VG(GATE1_3V)
VI(IN1) = 3 V
9
11.5
II(GATE1) = 500 nA,
VG(GATE1_4.5V)
Gate voltage
VI(IN1) = 4.5 V
10.5
14.5
V
DISCH1 open
VG(GATE1_10.8V)
VI(IN1) = 10.8 V
16.8
21
Clamping voltage, GATE1
VC(GATE1)
9
10
12
V
to DISCH1
3 V
≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
IS(GATE1)
Source current, GATE1
10
14
20
μA
VI(GATE1) = VI(IN1) + 6 V
3 V
≤ VI(IN1) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
Sink current, GATE1
50
75
100
µA
VI(GATE1) = VI(IN1)
VI(IN1) = 3 V
0.5
tr(GATE1)
Rise time, GATE1
Cg to GND = 1 nF
(1)
VI(IN1) = 4.5 V
0.6
ms
VI(IN1) = 10.8 V
1
VI(IN1) = 3 V
0.1
tf(GATE1)
Fall time, GATE1
Cg to GND = 1 nF
(1)
VI(IN1) = 4.5 V
0.12
ms
VI(IN1) = 10.8 V
0.2
GATE2
VG(GATE2_3V)
VI(IN2) = 3 V
9
11.7
II(GATE2) = 500 nA,
Gate voltage
V
DISCH2 open
VG(GATE2_4.5V)
VI(IN2) = 4.5 V
10.5
14.7
Clamping voltage, GATE2
VC(GATE2)
9
10
12
V
to DISCH2
3 V
≤ VI(IN2) ≤ 5.5 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
IS(GATE2)
Source current, GATE2
10
14
20
µA
VI(GATE2) = VI(IN2) + 6 V
3 V
≤ VI(IN2) ≤ 5.5 V, 3 V ≤ VO(VREG) ≤ 5.5 V,
Sink current, GATE2
50
75
100
µA
VI(GATE2) = VI(IN2)
VI(IN2) = 3 V
0.5
tr(GATE2)
Rise time, GATE2
Cg to GND = 1 nF
(1)
ms
VI(IN2) = 4.5 V
0.6
VO(VREG) = 3 V
VI(IN2) = 3 V
0.1
tf(GATE2)
Fall time, GATE2
Cg to GND = 1 nF
(1)
ms
VI(IN2) = 4.5 V
0.12
(1)
Specified, but not production tested.
Copyright © 2000–2013, Texas Instruments Incorporated
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