AD9863BCPZRL-501 datasheet(6/40 Pages) AD

No. de pieza	AD9863BCPZRL-501

Descripción Electrónicos	Mixed-Signal Front-End (MxFE) Baseband Transceiver for Broadband Applications

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AD9863

Rev. A| Page 6 of 40

TIMING SPECIFICATIONS

Table 5.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

INPUT CLOCK

CLKIN2 Clock Rate (PLL Bypassed)

Full

IV

1

200

MHz

PLL Input Frequency

Full

IV

16

200

MHz

PLL Ouput Frequency

Full

IV

32

350

MHz

TxPATH DATA

Setup Time

(HD24 Mode, Time Required Before Data Latching Edge)

Full

V

5

ns (see Clock

Distribution Block

section)

Hold Time

(HD24 Mode, Time Required After Data Latching Edge)

Full

V

−1.5

ns (see Clock

Distribution Block

section)

Latency 1× Interpolation (Data In Until Peak Output Response)

Full

V

7

DAC clock cycles

Latency 2× Interpolation (Data In Until Peak Output Response)

Full

V

35

DAC clock cycles

Latency 4× Interpolation (Data In Until Peak Output Response)

Full

V

83

DAC clock cycles

RxPATH DATA

Output Delay (HD24 Mode, tOD)

Full

V

−1.5

ns ( see Clock

Distribution Block

section)

Latency

Full

V

5

ADC clock cycles

Table 6. Explanation of Test Levels

Level

Description

I

100% production tested.

II

100% production tested at 25

°C and guaranteed by design and characterization at specified temperatures.

III

Sample tested only.

IV

Parameter is guaranteed by design and characterization testing.

V

Parameter is a typical value only.

VI

100% production tested at 25

°C and guaranteed by design and characterization for industrial temperature range.

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AD9863BCPZRL-501 Datasheet(PDF) 6 Page - Analog Devices

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