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ADG512 Datasheet(PDF) 8 Page - Analog Devices |
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ADG512 Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page ADG511/ADG512/ADG513 REV. C –8– VD OR VS – DRAIN OR SOURCE VOLTAGE – V 0.006 0.000 –0.006 –5 0.004 0.002 –0.002 –0.004 VDD = +5V VSS = –5V TA = +25 C ID (OFF) ID (ON) IS (OFF) –4 –3 –2 –1 0 1 234 5 TPC 7. Leakage Currents as a Function of VD (VS) FREQUENCY – Hz 110 100 60 100 10M 1k 10k 100k 1M 90 80 70 VDD = +5V VSS = –5V TPC 8. Crosstalk vs. Frequency APPLICATION Figure 1 illustrates a precise sample-and-hold circuit. An AD845 is used as the input buffer while the output operational ampli- fier is an OP07. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH. Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG511/ADG512/ ADG513 minimizes this droop due to its low leakage specifica- tions. The droop rate is further minimized by the use of a poly- styrene hold capacitor. The droop rate for the circuit shown is typically 15 µV/µs. A second switch, SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differen- tial effect on the op amp OP07, which will minimize charge injection effects. Pedestal error is also reduced by the compensation network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the ±3 V input range. The acquisition time is 2.5 µs while the settling time is 1.85 µs. +5V –5V 2200pF RC 75 CC 1000pF CH 2200pF VOUT ADG511/ ADG512/ ADG513 SW1 SW2 S S D D +5V –5V AD845 +5V –5V VIN OP07 Figure 1. Accurate Sample-and-Hold TRENCH ISOLATION The MOS devices that make up the ADG511A/ADG512A/ ADG513A are isolated from each other by an oxide layer (trench) (see Figure 2). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of “latch-up” caused by parasitic junctions between CMOS transistors. Latch-up is caused when P-N junctions that are normally reverse biased, become forward biased, causing large currents to flow. This can be destructive. CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation the N and P wells of the CMOS transistors form a diode that is reverse biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR)- type circuit is formed by the two transistors, causing a signifi- cant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up-proof circuit. BURIED OXIDE LAYER SUBSTRATE (BACKGATE) T R E N C H T R E N C H T R E N C H P+ P+ P-CHANNEL N+ N+ N-CHANNEL P– N– VG VD VS VG VD VS Figure 2. Trench Isolation |
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