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ADSP-BF533SBBC-500 Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-BF533SBBC-500 Datasheet(HTML) 11 Page - Analog Devices |
11 / 64 page ADSP-BF531/ADSP-BF532/ADSP-BF533 Rev. I | Page 11 of 64 | August 2013 PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be trig- gered by software interrupts. • GPIO interrupt sensitivity registers – The two GPIO inter- rupt sensitivity registers specify whether individual PFx pins are level- or edge-sensitive and specify—if edge-sensi- tive—whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. PARALLEL PERIPHERAL INTERFACE The processors provide a parallel peripheral interface (PPI) that can connect directly to parallel ADCs and DACs, video encod- ers and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate and the synchronization signals can be configured as either inputs or outputs. The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bi-directional data transfer with up to 16 bits of data. Up to three frame synchronization signals are also pro- vided. In ITU-R 656 mode, the PPI provides half-duplex bi- directional transfer of 8- or 10-bit video data. Additionally, on- chip decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported. General-Purpose Mode Descriptions The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct sub modes are supported: • Input mode – Frame syncs and data are inputs into the PPI. • Frame capture mode – Frame syncs are outputs from the PPI, but data are inputs. • Output mode – Frame syncs and data are outputs from the PPI. Input Mode Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_- CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit and 10-bit through 16-bit data, programmable in the PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hard- ware signaling. ITU-R 656 Mode Descriptions The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applica- tions. Three distinct sub modes are supported: •Active video only mode • Vertical blanking only mode • Entire field mode Active Video Only Mode Active video only mode is used when only the active video por- tion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in PPI_COUNT register). Vertical Blanking Interval Mode In this mode, the PPI only transfers vertical blanking interval (VBI) data. Entire Field Mode In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that can be embedded in horizontal and verti- cal blanking intervals. Data transfer starts immediately after synchronization to Field 1. Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core. DYNAMIC POWER MANAGEMENT The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pro- vides four operating modes, each with a different performance/ power profile. In addition, dynamic power management pro- vides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode. Full-On Operating Mode—Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum per- formance can be achieved. The processor core and all enabled peripherals run at full speed. |
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