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AD5142 Datasheet(PDF) 5 Page - Analog Devices |
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AD5142 Datasheet(HTML) 5 Page - Analog Devices |
5 / 28 page Data Sheet AD5123/AD5143 Rev. A | Page 5 of 28 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS9 Bandwidth BW −3 dB RAB = 10 kΩ 3 MHz RAB = 100 kΩ 0.43 MHz Total Harmonic Distortion THD VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ −80 dB RAB = 100 kΩ −90 dB Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ 7 nV/√Hz RAB = 100 kΩ 20 nV/√Hz VW Settling Time tS VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ 2 µs RAB = 100 kΩ 12 µs Crosstalk (CW1/CW2) CT RAB = 10 kΩ 10 nV-sec RAB = 100 kΩ 25 nV-sec Analog Crosstalk CTA −90 dB Endurance10 TA = 25°C 1 Mcycles 100 kcycles Data Retention11 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD). 9 All dynamic characteristics use VDD/VSS = ±2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. |
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