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MC10EP08 Datasheet(PDF) 2 Page - ON Semiconductor |
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MC10EP08 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 11 page MC10EP08, MC100EP08 http://onsemi.com 2 1 2 3 45 6 7 8 Q VEE VCC Figure 1. 8−Lead Pinout (Top View) and Logic Diagram D0 Q D1 D1 D0 Table 1. PIN DESCRIPTION PIN D0, D1, D0, D1 Q, Q ECL Data Outputs FUNCTION ECL Data Inputs D0* D1* D0** D1** Q Q LL H H L H LH H L H L HL L H H L HH L L L H Table 2. TRUTH TABLE VCC VEE Positive Supply Negative Supply * Pins will default LOW when left open. ** Pins will default to 0.666% of VCC when left open. EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg SOIC−8 TSSOP−8 DFN8 Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 135 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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