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ADS5520IPAPRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5520IPAPRG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 38 page Input Clock Analog Input Signal Sample N N + 1 N + 2 N + 3 N + 4 N + 1 4 N + 1 6 N + 1 7 N + 1 5 N − 17 N − 16 N − 15 N − 14 N − 13 N − 3 N − 2 N − 1 N tsu th tSTART tA tEND tPDI Data Out (D0−D11) 17.5 Clock Cycles Data Invalid Output Clock RESET TIMING CHARACTERISTICS RESET (Pin 35) t1 . 10 ms t2 . 2 ms t3 . 2 ms SEN Active Power Supply (AVDD, DRVDD) ADS5520 SBAS310F – MAY 2004 – REVISED OCTOBER 2008....................................................................................................................................................... www.ti.com A. It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. Figure 1. Timing Diagram Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD = DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification Power-on delay, t1 Delay from power-on of AVDD and 10 ms DRVDD to RESET pulse active Reset pulse width, t2 Pulse width of active RESET signal 2 µs Register write delay, t3 Delay from RESET disable to SEN 2 µs active Power-up time Delay from power-up of AVDD and 40 ms DRVDD to output stable Figure 2. Reset Timing Diagram 8 Submit Documentation Feedback Copyright © 2004–2008, Texas Instruments Incorporated Product Folder Link(s): ADS5520 |
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