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AKD4380 Datasheet(PDF) 3 Page - Asahi Kasei Microsystems |
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AKD4380 Datasheet(HTML) 3 Page - Asahi Kasei Microsystems |
3 / 21 page ASAHI KASEI [AKD4380] <KM061500> ’00/04 - 3 - 3) Using AKM’s evaluation board for ADC To evaluate AK4380 with analog input, the AKM’s evaluation board for ADC can be used. MCLK, BICK and LRCK are supplied from clock generator on the AKD4380, and analog signal is A/D converted and send to AKD4380 through PORT2(ADC/ROM). In case of using external master clock through a BNC connector, select “BNC” on JP12(MCLK) and short JP13(XTE). JP12 MCLK JP11 DIR JP3 BICK DIR ADC JP4 LRCK JP10 DIR_DATA JP9 SDTI DIR ADC GND VD DATA GND JP13 XTE 4) Feeding all signals from external Under the following set-up, all external signals can be fed through POTR2. JP12 MCLK JP11 DIR JP3 BICK DIR ADC JP4 LRCK JP10 DIR_DATA JP9 SDTI DIR ADC GND VD DATA GND JP13 XTE n Clock (MCLK,BICK,LRCK) set up In case of using evaluation mode 1), JP9,10 and 17 should be set up as follows. They need no care for other evaluation mode. MCLK JP5 (X_MCLK) JP8 (X_LRCK) BICK JP7 (X_BICK) 128fs 256/128 LR_128 32fs 64fs 64fs/32fs 128fs/64fs 256fs 256/128 LR_256/512 32fs 64fs 128fs 32fs 64fs/32fs 128fs/64fs default 512fs 512 LR_256/512 32fs 64fs 128fs 32fs 64fs/32fs 128fs/64fs Table 1. Clock set up |
Número de pieza similar - AKD4380 |
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Descripción similar - AKD4380 |
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