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CAT28F010GA-90T Datasheet(PDF) 1 Page - ON Semiconductor |
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CAT28F010GA-90T Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 16 page 1 Doc. No. MD-1019, Rev. G © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice DESCRIPTION The CAT28F010 is a high speed 128K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. It is pin and Read timing compatible with standard EPROM and EEPROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F010 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32-pin plastic DIP, 32-pin PLCC or 32-pin TSOP packages. BLOCK DIAGRAM FEATURES s Fast read access time: 90/120 ns s Low power CMOS dissipation: –Active: 30 mA max (CMOS/TTL levels) –Standby: 1 mA max (TTL levels) –Standby: 100 µA max (CMOS levels) s High speed programming: –10 µs per byte –2 Sec Typ Chip Program s 0.5 seconds typical chip-erase s 12.0V ± 5% programming and erase voltage s Stop timer for program/erase s Commercial, industrial and automotive temperature ranges s On-chip address and data latches s JEDEC standard pinouts: –32-pin DIP –32-pin PLCC –32-pin TSOP (8 x 20) s 100,000 program/erase cycles s 10 year data retention s Electronic signature I/O0–I/O7 I/O BUFFERS CE, OE LOGIC SENSE AMP DATA LATCH ERASE VOLTAGE SWITCH PROGRAM VOLTAGE SWITCH COMMAND REGISTER CE OE WE VOLTAGE VERIFY SWITCH Y-DECODER X-DECODER Y-GATING 1,048,576 BIT MEMORY ARRAY A0–A16 1 Megabit CMOS Flash Memory Licensed Intel second source CAT28F010 |
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