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CAT34TS04 Datasheet(PDF) 5 Page - ON Semiconductor |
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CAT34TS04 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 18 page CAT34TS04 http://onsemi.com 5 Figure 4. Acknowledge Timing ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER 30% 30% 70% 30% 70% 30% 30% 70% 70% 70% 70% 70% 70% SCL SDA IN Figure 5. Bus Timing tBUF tSU:STO tF tSU:STA tHD:STA tHD:DAT tSU:DAT tR tLOW tHIGH tDH SDA OUT 30% 70% Table 7. COMMAND SET (Notes 9, 10) Function Abbr Function Specific Preamble Select Address R/W_n A0 Pin b7 b6 b5 b4 b3 b2 b1 b0 Read Temperature Registers RTR 0 0 1 1 LSA2 LSA1 LSA0 1 0 or 1 Write Temperature Registers WTR 0 Read EE Memory RSPD 1 0 1 0 LSA2 LSA1 LSA0 1 0 or 1 Write EE Memory WSPD 0 Set Write Protection, block 0 SWP0 0 1 1 0 0 0 1 0 VHV Set Write Protection, block 1 SWP1 1 0 0 0 VHV Set Write Protection, block 2 SWP2 1 0 1 0 VHV Set Write Protection, block 3 SWP3 0 0 0 0 VHV Clear All Write Protection CWP 0 1 1 0 VHV Read Protection Status, block 0 RPS0 0 0 1 1 0, 1 or VHV Read Protection Status, block 1 RPS1 1 0 0 1 0, 1 or VHV Read Protection Status, block 2 RPS2 1 0 1 1 0, 1 or VHV Read Protection Status, block 3 RPS3 0 0 0 1 0, 1 or VHV Set SPD Page Address to 0 (Select Lower Bank) SPA0 1 1 0 0 0, 1 or VHV Set SPD Page Address to 1 (Select Upper Bank) SPA1 1 1 1 0 0, 1 or VHV Read SPD Page Address RPA 1 1 0 1 0, 1 or VHV Reserved − All Other Encodings 9. LSAx stands for Logic State of Address pin x. 10.If VHV is not applied on the A0 pin during SWP/CWP commands, the CAT34TS04 will respond with NoACK after the 3rd byte and will not execute the SWP/CWP instruction. During RPS/SPA/RPA commands the state of pin A0 must be stable for the duration of the sequence. |
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