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MC34937APEK Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MC34937APEK Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 49 page Analog Integrated Circuit Device Data 10 Freescale Semiconductor 34937A ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS CHARGE PUMP Charge Pump High Side Switch On Resistance Low Side Switch On Resistance Regulation Threshold Difference(17), (19) RDS(on)_HS RDS(on)_LS VTHREG – – 250 6.0 5.0 500 10 9.4 900 mV Charge Pump Output Voltage(18), (19) IOUT = 40 mA, 6.0 V < VSYS < 8.0 V IOUT = 40 mA, VSYS > = 8.0 V VCP 8.5 12 9.5 – – – V GATE DRIVE High Side Driver On Resistance (Sourcing) VPWR = VSUP = 16 V, -40 C TA 25 C VPWR = VSUP = 16 V, 25 C TA 125 C RDS(ON)_H_SRC – – – – 6.0 8.5 High Side Driver On Resistance (Sinking) VPWR = VSUP = 16 V RDS(ON)_H_SINK – – 3.0 High Side Current Injection Allowed Without Malfunction(19), (20) IHS_INJ – – 0.5 A Low Side Driver On Resistance (Sourcing) VPWR = VSUP = 16 V, -40 C TA 25 C VPWR = VSUP = 16 V, 25 C TA 125 C RDS(ON)_L_SRC – – – – 6.0 8.5 Low Side Driver On-Resistance (Sinking) VPWR = VSUP = 16 V RDS(ON)_L_SINK – – 3.0 Low Side Current Injection Allowed Without Malfunction(19), (20) ILS_INJ – – 0.5 Gate Source Voltage, VPWR = VSUP = 40 V High Side, IGATE = 0 (21) Low Side, IGATE = 0 VGS_H VGS_L 13 13 14.8 15.4 16.5 17 V Reverse High Side Gate Holding Voltage(22) Gate Output Holding Current = 2.0 µA Gate Output Holding Current = 5.0 µA, VSUP<26 V Gate Output Holding Current = 5.0 µA, VSUP<40 V VHS_G_HOLD – – – 10 10 – 15 15 15 V Notes 17. When VLS is this amount below the normal VLS linear regulation threshold, the charge pump is enabled. 18. VSYS is the system voltage on the input to the charge pump. Recommended external components: 1.0 µF MLC, MUR 120 diode. 19. This parameter is a design characteristic, not production tested. 20. Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of approximately 1.0 µs after an output switch transition. 1.0 µs is sufficient for all intended applications of this IC. 21. If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not recover completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap and the VLS capacitors. 22. High Side Gate Holding voltage is the voltage between the Gate and Source of the high side FET when held in an on condition. The trickle charge pump supplies bias and holding current for the High Side FET gate driver and output to maintain voltages after bootstrap events. See Figure 11 for typical 100% high side gate voltage with a 5.0 µA load. This parameter is a design characteristic, not production tested. Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V-40 C TA 125 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit |
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