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CAB4AZNRR Datasheet(PDF) 1 Page - Texas Instruments |
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CAB4AZNRR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 10 page DDR4 ² Memory Subsystem PLL Command Address Clock Clock Data CAB4A Data CPU / DSP / Ethernet MCU MEMORY CONTROLLER (MCH) CAB4A www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 CAB4A - DDR4 Register 32-Bit 1:2 Command/Address/Control Buffer and 1:4 Differential Clock Buffer Check for Samples: CAB4A 1 FEATURES DESCRIPTION The CAB4 is 32-bit 1:2 Command/Address/Control 23 • DDR4RCD01 JEDEC Compliant Buffer and 1:4 differential Clock Buffer designed for • DDR4 RDIMM and LRDIMM up to DDR4-2400 operation on DDR4 registered DIMMs with a 1.2 V • 32 Bits 1-to-2 Register Outputs VDD mode. • 1-to-4 Differential Clock Buffer All inputs are pseudo-differential using external or • 1.2V Operation internal voltage reference. All outputs are full swing CMOS drivers optimized to drive 15 to 50 Ω effective • PLL with Internal Feedback terminated traces in DDR4 RDIMM, LRDIMM and 3D- • Configurable Driver Strength Stacked DIMM applications. The clock outputs, • Scalable Weak Driver command/address outputs, control outputs, data buffer control outputs can be enabled in groups, and • Programmable Latency independently driven with different strengths to • Output Driver Calibration compensate for different DIMM net topologies. The • Address Mirroring and Inversion DDR4 Register operates from a differential clock (CK_t and CK_c). Inputs are registered at the • DDR4 Full-Parity Operation crossing of CK_t going HIGH, and CK_c going LOW. • On-Chip Programmable VREF Generation The input signals could be either re-driven to the • CA Bus Training Mode outputs if one of the input signals DCS[n:0]_n is driven LOW or it could be used to access device • I2C™ Interface Support internal control registers when certain input conditions • Up to 16-Logical Ranks Support for 3DS are met. RDIMMs and LRDIMMs The device is characterized in the operating • Up to 4 Physical Ranks Support for RDIMMs temperature range from -40°C to 95°C. and LRDIMMs Figure 1. DDR4 - RDIMM Memory Subsystem 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 I2C is a trademark of NXP Semiconductors. 3 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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