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TPS7A3501DRVT Datasheet(PDF) 11 Page - Texas Instruments |
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TPS7A3501DRVT Datasheet(HTML) 11 Page - Texas Instruments |
11 / 23 page TPS7A3501 www.ti.com SBVS228A – JULY 2013 – REVISED OCTOBER 2013 Power-Supply Rejection Ratio (PSRR) Unlike standard LDOs, the TPS7A3501 PSRR is significantly affected by the noise-reduction capacitor. The larger the noise-reduction capacitor, the higher the PSRR is for frequencies below 10 kHz. Using a 1- μF ceramic capacitor maximizes PSRR. One of the most compelling features of the TPS7A3501 is its high PSRR capabilities. The rejection ratio for this device is lower than standard LDOs at frequencies below 1 kHz but becomes higher at higher frequencies. For better low-frequency PSRR performance, a larger noise-reduction capacitor can be used. Connecting a 1-µF ceramic capacitor to NR is recommended to maximize PSRR (see Figure 13). A higher input-to-output voltage difference also increases the device rejection ratio. Although the device maximizes rejection ratio at 500 mV, high rejection ratio can still be achieved with as little as a 330-mV input-to-output voltage differential, unlike most standard LDOs. Startup Because adding a noise-reduction capacitor leads to the formation of an RC filter, startup time and the rate at which the device tracks VIN are increased. Thus, consider the tradeoff between startup time, noise, and PSRR when selecting a noise-reduction capacitor to use with the TPS7A3501. Use Equation 3 to calculate the typical startup time. T_startup = 250,000 × CNR (s) (3) Table 3 shows the effect of various noise-reduction capacitors on RMS noise (with a 100-Hz to 100-kHz bandwidth), PSRR (at 1 kHz), and startup time. Table 3. Effect of Various Filter Capacitors RMS NOISE START-UP TIME FILTER CAPACITOR (BW 100 kHz to 100 kHz) PSRR (at 1 kHz) (EN to 90% of VOUT) 1 µF 3.62 µV 60 dB 250 ms 100 nF 4.21 µV 40 dB 25 ms 10 nF 20.70 µV 20 dB 3 ms Transient Response Increasing the size of the output capacitor reduces overshoot and undershoot magnitude during transients; however this size increase also slows the recovery from these transients. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE Input and output capacitors should be placed as close to the device pins as possible. All components are recommended to be on the same side of the printed circuit board (PCB) as the device. Using long, thin traces or vias to connect the device to external components is highly discouraged because this practice leads to parasitic inductances, which in turn degrade noise, PSRR, and transient response. For an example layout, refer to the TPS7A3501EVM-547 Evaluation Module User Guide (SLVU921). Minimum Load The device is stable without an output load. Shutdown The enable pin (EN) is active high and compatible with standard and low-voltage TTL-CMOS levels. The enable pin voltage level is independent of input voltage and can be biased to a higher value than VIN as long as EN is within the maximum specification. When shutdown capability is not required, EN can be connected to IN. Internal Current Limit The device has an internal foldback current limit that helps protect the power filter during fault conditions. The current supplied by the device is gradually reduced when the output voltage decreases. When the output is shorted to GND, the LDO supplies a typical current of 550 mA. When in current limit, the output voltage is not regulated and VOUT = IOUT × RLOAD. For reliable operation, the device should not be operated in current limit for extended periods of time. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS7A3501 |
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