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TPS61282YFF Datasheet(PDF) 10 Page - Texas Instruments

No. de pieza TPS61282YFF
Descripción Electrónicos  Low-, Wide- Voltage Battery Front-End DC/DC Converter Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TPS61282YFF Datasheet(HTML) 10 Page - Texas Instruments

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SW
PGND
SDA
PGND
SW
nBYP
AGND
PGND
TOP VIEW
D4
D3
D2
D1
C4
PGND
C3
C2
C1
nBYP
PGND
SW
SDA
AGND
BOTTOM VIEW
VSEL
SCL
VOUT
VOUT
VOUT
B1
B2
B3
B4
VOUT
VSEL
SCL
EN
GPIO
VIN
VIN
VIN
A1
A2
A3
A4
VIN
EN
GPIO
SW
PGND
TPS61280
, TPS61281, TPS61282
SLVSBI1 – OCTOBER 2013
www.ti.com
PIN ASSIGNMENTS (TPS61280)
Table 1. PIN FUNCTIONS (TPS61280)
PIN
I/O
DESCRIPTION
NAME
NO.
VIN
A3, A4
I
Power supply input.
VOUT
B3, B4
O
Boost converter output.
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset
with their default values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled.
Depending on the logic level applied to the nBYP input, the converter can either be forced in pass-
EN
A1
I
through mode or it's output can be regulated to a minimum level so as to limit the input-to-output
voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For more
details, refer to Table 5.
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode
transition. For more details, refer to Table 5.
This pin can either be configured as a input (mode selection) or as dual role input/open-drain output
(nRST/nFAULT) pin. Per default, the pin is configured as nRST/nFAULT input/output. The input must
not be left floating and must be terminated.
Manual Reset Input: Drive nRST/nFAULT low to initiate a reset of the converter's output.
nRST/nFAULT controls a falling edge-triggered sequence consisting of a discharge phase of the
capacitance located at the converter's output followed by a start-up phase.
Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal
GPIO
A2
I/O
shutdown, output voltage out of limits, current limit triggered etc ...). To signal such an event, the
device generates a falling edge-triggered interrupt by driving a negative pulse onto the GPIO line and
then releases the line to its inactive state.
Mode selection input = Low: The device is operating in regulated frequency pulse width modulation
mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load
currents.
Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced.
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin
VSEL
B1
I
must not be left floating and must be terminated.
A logic low level on the nBYP input forces the device in pass-through mode. For more details, refer
nBYP
C1
I
to . This pin must not be left floating and must be terminated.
SCL
B2
I
Serial interface clock line. This pin must not be left floating and must be terminated.
SDA
C2
I/O
Serial interface address/data line. This pin must not be left floating and must be terminated.
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the
SW
C3, C4
I/O
inductor.
PGND
D2, D3, D4
Power ground pin.
AGND
D1
Analog ground pin. This is the signal ground reference for the IC.
10
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS61280 TPS61281 TPS61282


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