ADS7841

11

SBAS084B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(MSB)

(LSB)

S

A2

A1

A0

MODE

SGL/DIF

PD1

PD0

TABLE III. Order of the Control Bits in the Control Byte.

TABLE IV. Descriptions of the Control Bits within the

Control Byte.

BIT

NAME

DESCRIPTION

7

S

Start Bit. Control byte starts with first HIGH bit on

DIN. A new control byte can start every 15th clock

cycle in 12-bit conversion mode or every 11th clock

cycle in 8-bit conversion mode.

6 - 4

A2 - A0

Channel Select Bits. Along with the SGL/DIF bit,

these bits control the setting of the multiplexer input,

see Tables I and II.

3

MODE

12-Bit/8-Bit Conversion Select Bit. If the MODE pin

is HIGH, this bit controls the number of bits for the

next conversion: 12-bits (LOW) or 8-bits (HIGH). If

the MODE pin is LOW, this bit has no function and

the conversion is always 12 bits.

2

SGL/DIF

Single-Ended/Differential Select Bit. Along with bits

A2 - A0, this bit controls the setting of the multiplexer

input, see Tables I and II.

1 - 0

PD1 - PD0

Power-Down Mode Select Bits. See Table V for

details.

Control Byte

Also shown in Figure 3 is the placement and order of the

control bits within the control byte. Tables III and IV give

detailed information about these bits. The first bit, the ‘S’ bit,

must always be HIGH and indicates the start of the control

byte. The ADS7841 will ignore inputs on the DIN pin until

the start bit is detected. The next three bits (A2 - A0) select

the active input channel or channels of the input multiplexer

(see Tables I and II and Figure 2).

MODE pin is HIGH, then the MODE bit determines the

number of bits for each conversion, either 12 bits (LOW) or

8 bits (HIGH).

The SGL/DIF bit controls the multiplexer input mode: either

single-ended (HIGH) or differential (LOW). In single-ended

mode, the selected input channel is referenced to the COM

pin. In differential mode, the two selected inputs provide a

differential input. See Tables I and II and Figure 2 for more

information. The last two bits (PD1 - PD0) select the power-

down mode, as shown in Table V. If both inputs are HIGH,

the device is always powered up. If both inputs are LOW,

the device enters a power-down mode between conversions.

When a new conversion is initiated, the device will resume

normal operation instantly—no delay is needed to allow the

device to power up and the very first conversion will be

valid.

16-Clocks per Conversion

The control bits for conversion n+1 can be overlapped with

conversion ‘n’ to allow for a conversion every 16 clock

cycles, as shown in Figure 4. This figure also shows possible

serial communication occurring with other serial peripherals

between each byte transfer between the processor and the

converter. This is possible provided that each conversion

completes within 1.6ms of starting. Otherwise, the signal

that has been captured on the input sample-and-hold may

droop enough to affect the conversion result. In addition, the

ADS7841 is fully powered while other serial communica-

tions are taking place.

1

DCLK

CS

81

11

DOUT

BUSY

S

DIN

CONTROL BITS

S

CONTROL BITS

10

98765

4

3210

11 10

9

81

1

8

FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated

serial port.

PD1

PD0

Description

0

0

Power-down between conversions. When each

conversion is finished, the converter enters a low

power mode. At the start of the next conversion,

the device instantly powers up to full power. There

is no need for additional delays to assure full

operation and the very first conversion is valid.

0

1

Reserved for Future Use

1

0

Reserved for Future Use

1

1

No power-down between conversions, device al-

ways powered.

TABLE V. Power-Down Selection.

The MODE bit and the MODE pin work together to deter-

mine the number of bits for a given conversion. If the

MODE pin is LOW, the converter always performs a 12-bit

conversion regardless of the state of the MODE bit. If the