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HFC0300 Datasheet(PDF) 10 Page - Monolithic Power Systems

No. de Pieza. HFC0300
Descripción  Variable Off Time Controller
Descarga  21 Pages
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Fabricante  MPS [Monolithic Power Systems]
Página de inicio  http://www.monolithicpower.com
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HFC0300 Datasheet(HTML) 10 Page - Monolithic Power Systems

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HFC0300– VARIABLE OFF TIME CONTROLLER
HFC0300 Rev. 1.0
www.MonolithicPower.com
10
9/23/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
the output voltage decreases if the load
continues to increase. COMP then drops below
the over-load protection (OLP) point because
feedback is equivalent to an open circuit.
By continuously monitoring the COMP, when the
COMP voltage drops below 0.85V—which is
considered an error—the timer starts counting. If
the error flag is removed, the timer resets. If the
timer reaches completion at the delay time
determined by the FSET capacitor (for example,
74ms at CFSET=330pF), OLP takes place. This
timer avoids triggering OLP when the power
supply is at start-up or load transition phase.
Therefore the power supply should start-up in
less than over load protection delay time, as
determined by the following equation:
FSET
delay
C
t74ms
330pF

Short Circuit Protection
The HFC0300 shuts down when the CS voltage
rises higher than 1V using short-circuit protection
(SCP). As soon as the fault disappears, the
power supply resumes operation. During SCP,
the VCC UVLO lower threshold goes from 8.2V
to 5.5V.
Thermal Shutdown
The HFC0300 shuts down switching when the
inner temperature exceeds 150°C to prevent
damaging high temperatures
. As soon as the inner
temperature drops below 125°C, the power
supply resumes operation. During the thermal
shutdown (TSD), the VCC UVLO lower threshold
goes from 8.2V to 5.5V.
Peak current compression
As the load becomes lighter, the frequency
decreases and may enter the audible range. To
avoid exciting mechanical resonances in the
transformer and generating acoustic noise, the
HFC0300 reduces the peak current as power
goes down and thus reduces noise issues.
Figure 5 shows the curve of peak current versus
COMP.
COMP(V)
Peak
Current(V)
0.5
0.167
2.1
3.1
0.9
3.2
Constant
Peak Current
Peak Current
Compression
Burst
Mode
Figure 5: Peak Current vs. COMP
Burst Operation
The HFC0300 enters burst-mode operation to
minimize power dissipation in no load or light
load conditions. As the load decreases, the
COMP voltage increases; The IC stops switching
when the COMP voltage increases over the
threshold, VBRUH = 3.2V. The output voltage then
drops, which causes the COMP voltage to
decrease further. Once the COMP voltage falls
below the threshold VBRUL = 3.1V, switching
resumes and the COMP voltage then oscilates.
The burst mode operation alternately enables
and disables switching cycle of the MOSFET.
Leading-Edge Blanking
In order to avoid the premature termination of the
switching pulse due to the parasitic capacitance,
an internal leading-edge blanking (LEB) unit is
employed between the CS pin and the current
comparator input. During the blanking time, the
current comparator is disabled and can not turn
off the external MOSFET. Figure 6 shows the
leading-edge blanking.
TLEB=200nS
VLimit
t
Figure 6: Leading-Edge Blanking


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