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HFC0300 Datasheet(PDF) 14 Page - Monolithic Power Systems

No. de Pieza. HFC0300
Descripción  Variable Off Time Controller
Descarga  21 Pages
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Fabricante  MPS [Monolithic Power Systems]
Página de inicio  http://www.monolithicpower.com
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HFC0300 Datasheet(HTML) 14 Page - Monolithic Power Systems

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HFC0300– VARIABLE OFF TIME CONTROLLER
HFC0300 Rev. 1.0
www.MonolithicPower.com
14
9/23/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
IMOSFET
Ipeak
Ivalley
Figure 10: Primary Current at CCM
So the peak current can be determined as:
o
peak _ CCM
depth
2I
I
(1 D) (1 K
) N
 
(6)
Usually, BCM is preferable at power levels below
40W, and CCM is preferable at power levels
higher than 40W: The higher the power
delivered, the deeper the CCM adopted for
higher efficiency and better thermal performance
at full load. For example, for a 90W power
supply, Kdepth should be around 0.5.
The
converter
operation
mode
must
be
determined with each power supply specification
given; i.e. determine the Kdepth. Ipeak and Ivalley as
calculated by equations (3) through (6). Select
the current sense resistor using equation (7).
peak
sense
peak
V
R
I
(7)
Where Vpeak is the peak voltage threshold of the
current resistor; a constant 0.5V for HFC0300.
Chose the current resistor with the proper power
rating based on the power loss given in equation
(8)
peak
valley 22
sense
peak
valley
sense
II
1
P[(
)
(I
I
) ] D R
212

 
(8)
Design of CFSET and OLP Function
The capacitor CFSET sets the maximum frequency
as shown in equation (9). This capacitor is
charged by a constant-current source shortly
after the primary side switch turns on (about
0.6µs delay), and its voltage is compared with the
COMP voltage from feedback loop (see Figure
11).
When the capacitor voltage reaches threshold,
the capacitor rapidly discharges down to 0V, and
a new period starts. An internal delay of about
0.6µs delay before CFSET charges again fully
discharges the voltage at the FSET pin, (see
Figure 12). Thus the switching frequency is
regulated by the feedback loop like a voltage-
controlled oscillation (VCO).
max
FSET
1
28uA (
0.6us)
f
C
0.88V

(9)
Where fmax is the maximum frequency set by
the capacitor connected to FSET pin.
S
R
_
Q
Q
28µA
3.3V
VOFFSET
0.88V
0.6µs
pulse
Drive
FSET
COMP
VCC
Figure 11: Schematic for Voltage-Controlled
Oscillation
Maximum Frequency
Minimum Frequency
IFSET=28µA
Vfset
Controlled by the
COMP Voltage
Pout Decrease
Pout Increase
Figure 12: Switching Frequency as Adjusted
by COMP Voltage
As described in the section above, the switching
frequency reaches its maximum at low line and
full load. This frequency, defined as fs (65kHz in
this case). Set the maximum frequency (fmax) at
110% fs. The frequency increases with the
increasing output power. When the frequency
reaches its maximum—set by CFSET—the over-
power limit drops the output voltage, saturating
COMP, and drops the OLP threshold (0.85V).
The OLP uses a unique digital timer method:
When COMP is less than 0.85V and raises an
error flag, the timer starts counting. If the error
flag is removed, the timer resets. If the timer
overflows after reaching 6000, OLP triggers. This
timer duration avoids triggering the OLP when


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