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## HFC0300 Datasheet(PDF) 14 Page - Monolithic Power Systems

 No. de Pieza. HFC0300 Descripción Variable Off Time Controller Descarga 21 Pages Scroll/Zoom 100% Fabricante MPS [Monolithic Power Systems] Página de inicio http://www.monolithicpower.com Logo

## HFC0300 Datasheet(HTML) 14 Page - Monolithic Power Systems

 14 / 21 page HFC0300– VARIABLE OFF TIME CONTROLLERHFC0300 Rev. 1.0www.MonolithicPower.com149/23/2011MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.© 2011 MPS. All Rights Reserved.IMOSFETIpeakIvalleyFigure 10: Primary Current at CCMSo the peak current can be determined as:opeak _ CCMdepth2II(1 D) (1 K) N (6)Usually, BCM is preferable at power levels below40W, and CCM is preferable at power levelshigher than 40W: The higher the powerdelivered, the deeper the CCM adopted forhigher efficiency and better thermal performanceat full load. For example, for a 90W powersupply, Kdepth should be around 0.5.Theconverteroperationmodemustbedetermined with each power supply specificationgiven; i.e. determine the Kdepth. Ipeak and Ivalley ascalculated by equations (3) through (6). Selectthe current sense resistor using equation (7).peaksensepeakVRI(7)Where Vpeak is the peak voltage threshold of thecurrent resistor; a constant 0.5V for HFC0300.Chose the current resistor with the proper powerrating based on the power loss given in equation(8)peakvalley 22sensepeakvalleysenseII1P[()(II) ] D R212 (8)Design of CFSET and OLP FunctionThe capacitor CFSET sets the maximum frequencyas shown in equation (9). This capacitor ischarged by a constant-current source shortlyafter the primary side switch turns on (about0.6µs delay), and its voltage is compared with theCOMP voltage from feedback loop (see Figure11).When the capacitor voltage reaches threshold,the capacitor rapidly discharges down to 0V, anda new period starts. An internal delay of about0.6µs delay before CFSET charges again fullydischarges the voltage at the FSET pin, (seeFigure 12). Thus the switching frequency isregulated by the feedback loop like a voltage-controlled oscillation (VCO).maxFSET128uA (0.6us)fC0.88V(9)Where fmax is the maximum frequency set bythe capacitor connected to FSET pin.SR_QQ28µA3.3VVOFFSET0.88V0.6µspulseDriveFSETCOMPVCCFigure 11: Schematic for Voltage-ControlledOscillationMaximum FrequencyMinimum FrequencyIFSET=28µAVfsetControlled by theCOMP VoltagePout DecreasePout IncreaseFigure 12: Switching Frequency as Adjustedby COMP VoltageAs described in the section above, the switchingfrequency reaches its maximum at low line andfull load. This frequency, defined as fs (65kHz inthis case). Set the maximum frequency (fmax) at110% fs. The frequency increases with theincreasing output power. When the frequencyreaches its maximum—set by CFSET—the over-power limit drops the output voltage, saturatingCOMP, and drops the OLP threshold (0.85V).The OLP uses a unique digital timer method:When COMP is less than 0.85V and raises anerror flag, the timer starts counting. If the errorflag is removed, the timer resets. If the timeroverflows after reaching 6000, OLP triggers. Thistimer duration avoids triggering the OLP when