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ADSP-BF514KSWZ-3 Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-BF514KSWZ-3 Datasheet(HTML) 6 Page - Analog Devices |
6 / 68 page Rev. B | Page 6 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F The processors internally connect to the flash memory die with the SPI0SCK, SPI0SEL4 or PH8, SPI0MOSI, and SPI0MISO sig- nals similar to an external SPI flash. To further provide a secure processing environment, these internally connected signals are not exposed outside of the package. For this reason, program- ming the ADSP-BF51xF flash memory is performed by running code on the processor andcannot be programmed from external signals. Data transfers between the SPI flash and the processor cannot be probed externally. The flash memory has the follow- ing additional features • Serial Interface Architecture—SPI compatible with Mode 0 and Mode 3 • Superior Reliability—Endurance of 100,000 cycles and greater than 100 years data retention • Flexible Erase Capability—Uniform 4K Byte sectors and uniform 32 and 64K Byte overlay blocks • Fast Erase and Byte-Program—Chip-erase time = 125 ms (typical), Sector-/Block-Erase Time = 62 ms (typical) Byte- Program Time = 50 μS (typical) • Auto Address Increment (AAI) Programming—Decreases total chip programming time over byte-program operations • End-of-Write Detection—Software polling the BUSY bit in status register, busy status readout on SO pin • Software Write Protection—Write protection through block-protection bits in status register One-Time Programmable Memory The processors have 64K bits of one-time programmable non- volatile memory that can be programmed by the developer only once. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. The OTP memory allows both public and private data to be stored on-chip. In addition to storing public and private key data for applications requiring security, OTP allows developers to store completely user-definable data such as customer ID, product ID, and MAC address. Therefore, generic parts can be supplied which are then programmed and protected by the developer within this non-volatile memory. I/O Memory Space The processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory- mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting from ROM The processors contain a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. If the processors are configured to boot from boot ROM memory space, the pro- cessor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 14. EVENT HANDLING The event controller handles all asynchronous and synchronous events to the processor. The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events: • Emulation—An emulation event causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface. • Reset—This event resets the processor. • Nonmaskable Interrupt (NMI)—The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions—Events that occur synchronously to program flow; that is, the exception is taken before the instruction is allowed to complete. Conditions such as data alignment violations and undefined instructions cause exceptions. •Interrupts—Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The event controller consists of two stages, the core event con- troller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, inter- rupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processors. The inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities are described in the ADSP-BF51x Blackfin Processor Hardware Reference Manual “System Interrupts” chapter. |
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