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LM4550BVHX Datasheet(PDF) 5 Page - Texas Instruments |
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LM4550BVHX Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 43 page  LM4550B www.ti.com SNAS276F – MAY 2005 – REVISED APRIL 2013 Electrical Characteristics (1)(2) (continued) The following specifications apply for AVDD = 5V, DVDD = 3.3V, Fs = 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. LM4550B Units Symbol Parameter Conditions (Limits) Typical(3) Limit(4) Digital I/O(10) 0.65 x VIH High level input voltage V (min) DVDD 0.35 x VIL Low level input voltage V (max) DVDD 0.90 x VOH High level output voltage IO = −2.5 mA. V (min) DVDD 0.10 x VOL Low level output voltage IO = 2.5 mA. V (max) DVDD IL Input Leakage Current AC Link inputs ±10 µA IL Tri state Leakage Current High impedance AC Link outputs ±10 µA Cin AC-Link I/O capacitance SDout, BitClk, SDin, Sync, Reset# only 4 7.5 pF (max) IDR Output drive current AC Link outputs 5 mA Digital Timing Specifications(10) FBC BIT_CLK frequency 12.288 MHz TBCP BIT_CLK period 81.4 ns TCH BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20 % (max) FSYNC SYNC frequency 48 kHz TSP SYNC period 20.8 µs TSH SYNC high pulse width 1.3 µs TSL SYNC low pulse width 19.5 µs TDSETUP Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 3.5 10 ns (min) Hold time of SDATA_OUT from falling edge TDHOLD Hold Time for codec data input 5.3 10 ns (min) of BIT_CLK(10) TSSETUP Setup Time for codec SYNC input SYNC to falling edge of BIT_CLK(10) 3.8 10 ns (min) Hold time of SYNC from falling edge of TSHOLD Hold Time for codec SYNC input 10 ns (min) BIT_CLK Output Delay of SDATA_IN from rising edge TCO Output Valid Delay 5.2 15 ns (max) of BIT_CLK(10) TRISE Rise Time BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 ns (max) TFALL Fall Time BIT_CLK, SYNC, SDATA_IN or SDATA_OUT 6 ns (max) Data Delay from CIN to SDATA_IN when the TCS Chain Propagation Delay ns (max) chain feature is active TRST_LOW RESET# active low pulse width For Cold Reset 1.0 µs (min) TRST2CLK RESET# inactive to BIT_CLK start up For Cold Reset 271 162.8 ns (min) TSH SYNC active high pulse width For Warm Reset 1.0 µs (min) TSYNC2CLK SYNC inactive to BIT_CLK start up For Warm Reset 162.8 ns (min) Delay from end of Slot 2 to BIT_CLK, TS2_PDOWN AC Link Power Down Delay 1 µs (max) SDATA_IN low Time from minimum valid supply levels to end TSUPPLY2RST Power On Reset 1 µs (min) of Reset TSU2RST Setup to trailing edge of RESET# For ATE Test Mode 15 ns (min) TRST2HZ Rising edge of RESET# to Hi-Z For ATE Test Mode 25 ns (max) (10) These specifications are ensured by design and characterization; they are not production tested. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM4550B |
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