AD9516-5BCPZ datasheet(1/76 Pages) AD

No. de pieza	AD9516-5BCPZ

Descripción Electrónicos	14-Output Clock Generator

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14-Output Clock Generator

AD9516-5

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Low phase noise, phase-locked loop (PLL)

External VCO/VCXO to 2.4 GHz optional

1 differential or 2 single-ended reference inputs

Reference monitoring capability

Automatic revertive and manual reference

switchover/holdover modes

Accepts LVPECL, LVDS, or CMOS references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

Six 1.6 GHz LVPECL outputs, arranged in 3 groups

Each group shares a 1-to-32 divider with coarse phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs of <10 ps

Four 800 MHz LVDS outputs, arranged in 2 groups

Each group has 2 cascaded 1-to-32 dividers with coarse

phase delay

Additive output jitter: 275 fs rms

Fine delay adjust (Δt) on each LVDS output

Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up

Manual output synchronization available

Available in 64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9516-51 provides a multi-output clock distribution function

with subpicosecond jitter performance, along with an on-chip PLL

that can be used with an external VCO/VCXO of up to 2.4 GHz.

The AD9516-5 emphasizes low jitter and phase noise to

maximize data converter performance, and it can benefit other

applications with demanding phase noise and jitter requirements.

FUNCTIONAL BLOCK DIAGRAM

REFIN

REF1

REF2

CLK

REFIN

CLK

DIVIDER

AND MUXes

CP

STATUS

MONITOR

LVPECL

LVDS/CMOS

SERIAL CONTROL PORT

AND

DIGITAL LOGIC

AD9516-5

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

DIV/Φ

∆t

Figure 1.

The AD9516-5 features six LVPECL outputs (in three pairs)

and four LVDS outputs (in two pairs). Each LVDS output can

be reconfigured as two CMOS outputs. The LVPECL outputs

operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and

the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide ratio

and coarse delay (or phase) to be set. The range of division for

the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow

a range of divisions up to a maximum of 1024.

The AD9516-5 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated by

connecting the charge pump supply (VCP) to 5.5 V. A separate

LVPECL power supply can be from 2.375 V to 3.6 V (nominal).

The AD9516-5 is specified for operation over the industrial

range of −40°C to +85°C.

For applications requiring an integrated EEPROM, or needing

additional outputs, the AD9520-5 and AD9522-5 are available.

1 AD9516 is used throughout the data sheet to refer to all members of the AD9516

family. However, when AD9516-5 is used, it refers to that specific member of the

AD9516 family.

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