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AD9549APCBZ Datasheet(PDF) 10 Page - Analog Devices

No. de pieza AD9549APCBZ
Descripción Electrónicos  Dual Input Network Clock Generator/Synchronizer
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9549APCBZ Datasheet(HTML) 10 Page - Analog Devices

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AD9549
Rev. D | Page 10 of 76
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVDD_I/O
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
S1
S2
AVDD
REFA_IN
REFA_INB
AVDD3
REFB_IN
REFB_INB
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL DIE ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
DAC_RSET
AVDD3
AVDD3
AVDD
AVDD
AVSS
AVDD
FDBK_IN
FDBK_INB
AVSS
OUT_CMOS
AVDD3
AVDD
OUT
OUTB
AVSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9549
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
1
I
Power
DVDD_I/O
I/O Digital Supply.
2, 4, 6, 8
I
Power
DVSS
Digital Ground. Connect to ground.
3, 5, 7
I
Power
DVDD
Digital Supply.
9, 10, 54, 55
I/O
3.3 V CMOS
S1, S2, S3, S4
Configurable I/O Pins. These pins are configured under program control (see
the Status and Warnings section) and do not have internal pull-up/pull-down
resistors.
11, 19, 23 to
26, 29, 30, 36,
42, 44, 45, 53
I
Power
AVDD
Analog Supply. Connect to a nominal 1.8 V supply.
12
I
Differential
input
REFA_IN
Frequency/Phase Reference A Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
13
I
Differential
input
REFA_INB
Complementary Frequency/Phase Reference A Input. Complementary signal
to the input provided on Pin 12. If using a single-ended, dc-coupled CMOS
signal into REFA_IN, bypass this pin to ground with a 0.01 μF capacitor.
14, 46, 47, 49
I
Power
AVDD3
Analog Supply. Connect to a nominal 3.3 V supply.
15
I
Differential
input
REFB_IN
Frequency/Phase Reference B Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
16
I
Differential
input
REFB_INB
Complementary Frequency/Phase Reference B Input. Complementary signal
to the input provided on Pin 15. If using a single-ended, dc-coupled CMOS
signal into REFB_IN, bypass this pin to ground with a 0.01 μF capacitor.
17, 18
NC
No Connect. These are excess, unused pins that can be left floating.


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