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ADP3301 Datasheet(PDF) 6 Page - Analog Devices |
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ADP3301 Datasheet(HTML) 6 Page - Analog Devices |
6 / 8 page ADP3303 –6– REV. A THEORY OF OPERATION The new anyCAP LDO ADP3303 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2, which is varied to provide the available output voltage options. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. gm PTAT VOS R4 R3 D1 R1 ATTENUATION (VBANDGAP/VOUT) R2 (a) COMPENSATION CAPACITOR NONINVERTING WIDEBAND DRIVER Q1 IN CLOAD OUT ADP3303 RLOAD PTAT CURRENT GND Figure 20. Functional Block Diagram A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature proportional input “offset voltage” that is repeatable and very well controlled. The temperature- proportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibil- ity on the tradeoff of noise sources that leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1, and a second divider consist- ing of R3 and R4, the values are chosen to produce a tempera- ture stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from base current loading in conventional circuits is avoided. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and ESR of the load capacitance. Most LDOs place strict requirements on the range of ESR val- ues for the output capacitor because they are difficult to sta- bilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. This is no longer true with the ADP3303 anyCAP LDO. It can be used with virtually any capacitor, with no constraint on the minimum ESR. The innovative design allows the circuit to be stable with just a small 0.47 µF capacitor on the output. Addi- tional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain, which leads to excel- lent line and load regulation. An impressive ±1.4% accuracy is guaranteed over line, load and temperature. Additional features of the circuit include current limit, thermal shutdown and noise reduction. Compared to standard solutions that give warning after the output has lost regulation, the ADP3303 provides improved system performance by enabling the ERR Pin to give warning before the device loses regulation. As the chip’s temperature rises above 165 °C, the circuit acti- vates a soft thermal shutdown, indicated by a signal low on the ERR Pin, to reduce the current to a safe level. To reduce the noise gain of the loop, the node of the main di- vider network (a) is made available at the noise reduction (NR) pin, which can be bypassed with a small capacitor (10 nF–100 nF). APPLICATION INFORMATION Capacitor Selection Output Capacitors: as with any micropower device, output transient response is a function of the output capacitance. The ADP3303 is stable with a wide range of capacitor values, types and ESR. A capacitor as low as 0.47 µF is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3303 is stable with extremely low ESR capacitors (ESR ≈ 0), such as Multilayer Ceramic Capacitors (MLCC) or OSCON. Input Bypass Capacitor: an input bypass capacitor is not required; for applications where the input source is high imped- ance or far from the input pins, a bypass capacitor is recom- mended. Connecting a 0.47 µF capacitor from the input pins to ground reduces the circuit’s sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended. Noise Reduction A noise reduction capacitor (CNR) can be used to further reduce the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in the 10 nF–100 nF range provide the best performance. Since the noise reduction pin (NR) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible. Long PC board traces are not recommended. IN OUT ERR GND ADP3303-5.0 NR + 6 7 8 1 2 3 4 5 ON OFF + SD CNR 10nF C2 10 F R1 330k EOUT C1 1 F VOUT = 5V VIN SD Figure 21. Noise Reduction Circuit |
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